From: Ilkka Koskinen <ilkka@os•amperecomputing.com>
To: Aviv Bakal <avivb@amazon•com>
Cc: robin.murphy@arm•com, will@kernel•org, mark.rutland@arm•com,
linux-arm-kernel@lists•infradead.org,
linux-perf-users@vger•kernel.org, linux-kernel@vger•kernel.org,
zeev@amazon•com, blakgeof@amazon•com,
ilkka@os•amperecomputing.com
Subject: Re: [PATCH v4 2/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5
Date: Mon, 1 Jun 2026 22:55:30 -0700 (PDT) [thread overview]
Message-ID: <bc40f7e8-0576-de20-c5ed-59ed10beb012@os.amperecomputing.com> (raw)
In-Reply-To: <20260531110447.10095-3-avivb@amazon.com>
On Sun, 31 May 2026, Aviv Bakal wrote:
> Graviton5 uses a customised CMN-S3 implementation where certain
> discovery registers report zeroed fields. Add the following workarounds:
>
> - Introduce a dedicated ACPI HID to identify the Graviton5 CMN variant.
> - Derive the DTC domain from the XP node ID, since the unit info
> register reports it as zero.
> - Set the DTC logical ID from the XP's logical ID, since the node info
> register's logical ID field is also zeroed.
>
> Signed-off-by: Aviv Bakal <avivb@amazon•com>
Thanks for the patch. It seems surprisingly clean approach. And thanks to
Robin for answering to Sashiko bot!
The patch looks good to me,
Reviewed-by: Ilkka Koskinen <ilkka@os•amperecomputing.com>
Cheers, Ilkka
> ---
> drivers/perf/arm-cmn.c | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c
> index f1978a53d1c1..3fb71d9a57eb 100644
> --- a/drivers/perf/arm-cmn.c
> +++ b/drivers/perf/arm-cmn.c
> @@ -31,7 +31,8 @@
> #define CMN_CHILD_NODE_ADDR GENMASK(29, 0)
> #define CMN_CHILD_NODE_EXTERNAL BIT(31)
>
> -#define CMN_MAX_DIMENSION 12
> +/* Some implementations use a mesh larger than the architectural max of 12 */
> +#define CMN_MAX_DIMENSION 14
> #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)
> #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
>
> @@ -214,6 +215,8 @@ enum cmn_part {
> PART_CMN700 = 0x43c,
> PART_CI700 = 0x43a,
> PART_CMN_S3 = 0x43e,
> + /* Synthetic part number, overridden to PART_CMN_S3 during discovery */
> + PART_GRAVITON5 = 0xa5,
> };
>
> /* CMN-600 r0px shouldn't exist in silicon, thankfully */
> @@ -2250,6 +2253,18 @@ static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_reg
> return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset));
> }
>
> +static unsigned int arm_cmn_graviton5_dtc_domain(u16 xp_id)
> +{
> + unsigned int x = (xp_id >> 7) & 0xf;
> + unsigned int y = (xp_id >> 3) & 0xf;
> +
> + /*
> + * The unit info register reads as zero; derive the DTC domain from
> + * the XP's mesh coordinates over the 10x14 mesh.
> + */
> + return (x / 5) + (y / 7) * 2;
> +}
> +
> static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
> {
> int level;
> @@ -2295,6 +2310,7 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
> u64 reg;
> int i, j;
> size_t sz;
> + bool graviton5_workaround = false;
>
> arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
> if (cfg.type != CMN_TYPE_CFG)
> @@ -2305,6 +2321,13 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
> reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
> part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg);
> part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8;
> +
> + /* Graviton5 has a customised CMN-S3 which needs some fixups */
> + if (cmn->part == PART_GRAVITON5) {
> + cmn->part = PART_CMN_S3;
> + graviton5_workaround = true;
> + }
> +
> /* 600AE is close enough that it's not really worth more complexity */
> if (part == PART_CMN600AE)
> part = PART_CMN600;
> @@ -2394,6 +2417,8 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
>
> if (cmn->part == PART_CMN600)
> xp->dtc = -1;
> + else if (graviton5_workaround)
> + xp->dtc = arm_cmn_graviton5_dtc_domain(xp->id);
> else
> xp->dtc = arm_cmn_dtc_domain(cmn, xp_region);
>
> @@ -2472,6 +2497,10 @@ static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
>
> switch (dn->type) {
> case CMN_TYPE_DTC:
> + if (graviton5_workaround) {
> + /* Node info logical ID is zeroed; use the XP's */
> + dn->logid = xp->logid;
> + }
> cmn->num_dtcs++;
> dn++;
> break;
> @@ -2687,6 +2716,7 @@ static const struct acpi_device_id arm_cmn_acpi_match[] = {
> { "ARMHC650" },
> { "ARMHC700" },
> { "ARMHC003" },
> + { "AMZN0070", PART_GRAVITON5 },
> {}
> };
> MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
> --
> 2.47.3
>
>
next prev parent reply other threads:[~2026-06-02 5:55 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-03 15:51 [PATCH] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5 Aviv Bakal
2026-05-04 13:39 ` [PATCH v2] " Aviv Bakal
2026-05-05 2:31 ` kernel test robot
2026-05-21 16:02 ` Robin Murphy
2026-05-24 15:38 ` [PATCH v3 0/2] " Aviv Bakal
2026-05-24 15:38 ` [PATCH v3 1/2] perf/arm-cmn: Move struct arm_cmn_hw_event into struct hw_perf_event Aviv Bakal
2026-05-29 16:44 ` Robin Murphy
2026-05-24 15:38 ` [PATCH v3 2/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5 Aviv Bakal
2026-05-31 11:04 ` [PATCH v4 0/2] " Aviv Bakal
2026-05-31 11:04 ` [PATCH v4 1/2] perf/arm-cmn: Move DTM index data out of hw_perf_event Aviv Bakal
2026-06-01 18:23 ` Robin Murphy
2026-06-02 5:49 ` Ilkka Koskinen
2026-05-31 11:04 ` [PATCH v4 2/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5 Aviv Bakal
2026-06-01 17:48 ` Robin Murphy
2026-06-02 5:55 ` Ilkka Koskinen [this message]
2026-06-03 15:00 ` [PATCH v5 0/2] " Aviv Bakal
2026-06-03 15:00 ` [PATCH v5 1/2] perf/arm-cmn: Move DTM index data out of hw_perf_event Aviv Bakal
2026-06-03 15:00 ` [PATCH v5 2/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5 Aviv Bakal
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