Subject: Re: [PATCH/RFC 10/14] dt-bindings: power: Document Renesas R-Car X5H Module Controller

From: Marek Vasut <[email-masked]>
Date: Thu, 7 May 2026 00:58:31 +0200

On 4/21/26 8:11 PM, Geert Uytterhoeven wrote:

Hello Geert,

> +  '#power-domain-cells':
> +    description: |
> +      - The first power domain specifier cell must be either the Module
> +        Power Domain Gating (MPDG) register index (0x00-0x3f) from the
> +        datasheet,

I agree with this part.

> or a Power Domain number, as defined in
> +        <dt-bindings/power/renesas,r8a78000-mdlc.h>,

I do not understand this part, please see end of this email ...

> +      - The second power domain specifier cell must be the module number
> +        (0x00-0xff), composed of the Module System Reset (MSRES) register index
> +        in the high nibble, and the Module Reset Destination bitfield index in
> +        the low nibble.
> +    const: 2

I am unsure about this part.

There are multiple MDLC blocks, AON, SCP, HSCN, and so on. Each MDLC 
block contains multiple Module Power Domain Gating registers (MPDGn) and 
multiple Module System RESet register (MSRES) .

I do understand and agree that the first power-domains-cells cell must 
be the identifier of power domain within the MDLC block.

However, I do not understand the second cell. The MDLC bindings already 
contain reset-cells, which should be used to refer to a reset within the 
MDLC block. Resets within the MDLC block are operated using the MSRES 
registers. Why are resets conflated into power-domain-cells ?

> +  '#reset-cells':
> +    description:
> +      The single reset specifier cell must be the module number (0x00-0xff).
> +    const: 1

[...]

> +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__
> +#define __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__
> +
> +/* R-Car X5H MDLC Power Domains */
> +
> +#define R8A78000_MDLC_PD_AON			0x40
> +#define R8A78000_MDLC_PD_SCP			0x41
> +#define R8A78000_MDLC_PD_APL			0x42
> +#define R8A78000_MDLC_PD_CMN			0x43
> +#define R8A78000_MDLC_PD_ACL			0x44
... what do these numbers represent ? Shouldn't those be register 
offsets from MDLC MPDG00 according to power-domain-cells ?

If those are power domain IDs, then I am unsure why e.g. for SCIF the 
domain ID is R8A78000_MDLC_PD_APL in [PATCH/RFC 13/14] arm64: dts: 
renesas: r8a78000: Add CPG/MDLC nodes . Could you please expand on that ?

Thank you !