Re: [PATCHv3 7/7] drm/msm/a6xx: Add support for using system cache(LLC)

From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora•org>
To: Rob Clark <robdclark@gmail•com>
Cc: Jordan Crouse <jcrouse@codeaurora•org>,
	Will Deacon <will@kernel•org>, David Airlie <airlied@linux•ie>,
	Sean Paul <sean@poorly•run>, Joerg Roedel <joro@8bytes•org>,
	Linux Kernel Mailing List <linux-kernel@vger•kernel.org>,
	dri-devel <dri-devel@lists•freedesktop.org>,
	Akhil P Oommen <akhilpo@codeaurora•org>,
	Emil Velikov <emil.velikov@collabora•com>,
	"list@263•net:IOMMU DRIVERS , Joerg Roedel <joro@8bytes•org>,
	" <iommu@lists•linux-foundation.org>,
	Matthias Kaehlcke <mka@chromium•org>,
	"Kristian H . Kristensen" <hoegsberg@google•com>,
	Daniel Vetter <daniel@ffwll•ch>,
	linux-arm-msm <linux-arm-msm@vger•kernel.org>,
	Stephen Boyd <swboyd@chromium•org>,
	freedreno <freedreno@lists•freedesktop.org>,
	Sharat Masetty <smasetty@codeaurora•org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists•infradead.org>,
	Robin Murphy <robin.murphy@arm•com>
Subject: Re: [PATCHv3 7/7] drm/msm/a6xx: Add support for using system cache(LLC)
Date: Fri, 03 Jul 2020 22:29:16 +0530	[thread overview]
Message-ID: <c925406446bb2f6c7aead8e047672cae@codeaurora.org> (raw)
In-Reply-To: <CAF6AEGsCROVTsi2R7_aUkmH9Luoc_guMR0w0KUJc2cEgpfj79w@mail.gmail.com>

On 2020-07-03 21:34, Rob Clark wrote:
> On Fri, Jul 3, 2020 at 7:53 AM Sai Prakash Ranjan
> <saiprakash.ranjan@codeaurora•org> wrote:
>> 
>> Hi Will,
>> 
>> On 2020-07-03 19:07, Will Deacon wrote:
>> > On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
>> >> diff --git a/drivers/gpu/drm/msm/msm_iommu.c
>> >> b/drivers/gpu/drm/msm/msm_iommu.c
>> >> index f455c597f76d..bd1d58229cc2 100644
>> >> --- a/drivers/gpu/drm/msm/msm_iommu.c
>> >> +++ b/drivers/gpu/drm/msm/msm_iommu.c
>> >> @@ -218,6 +218,9 @@ static int msm_iommu_map(struct msm_mmu *mmu,
>> >> uint64_t iova,
>> >>              iova |= GENMASK_ULL(63, 49);
>> >>
>> >>
>> >> +    if (mmu->features & MMU_FEATURE_USE_SYSTEM_CACHE)
>> >> +            prot |= IOMMU_SYS_CACHE_ONLY;
>> >
>> > Given that I think this is the only user of IOMMU_SYS_CACHE_ONLY, then
>> > it
>> > looks like it should actually be a property on the domain because we
>> > never
>> > need to configure it on a per-mapping basis within a domain, and
>> > therefore
>> > it shouldn't be exposed by the IOMMU API as a prot flag.
>> >
>> > Do you agree?
>> >
>> 
>> GPU being the only user is for now, but there are other clients which
>> can use this.
>> Plus how do we set the memory attributes if we do not expose this as
>> prot flag?
> 
> It does appear that the downstream kgsl driver sets this for basically
> all mappings.. well there is some conditional stuff around
> DOMAIN_ATTR_USE_LLC_NWA but it seems based on the property of the
> domain.  (Jordan may know more about what that is about.)  But looks
> like there are a lot of different paths into iommu_map in kgsl so I
> might have missed something.
> 
> Assuming there isn't some case where we specifically don't want to use
> the system cache for some mapping, I think it could be a domain
> attribute that sets an io_pgtable_cfg::quirks flag
> 

Ok then we are good to remove unused sys cache prot flag which Will has 
posted.

Thanks,
Sai

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