Subject: [PATCH v2 0/3] clk: mediatek: fix gate-less mux definitions

From: Daniel Golle <[email-masked]>
Date: Thu, 26 Mar 2026 05:09:22 +0000

Some MediaTek clock drivers define gate-less muxes without an update
register using MUX_GATE_CLR_SET_UPD, passing -1 as a sentinel for the
absent gate and update fields.  Since those fields are stored in u8 and
u32 struct members, the -1 truncates to unexpected values.

Add MUX_CLR_SET, a wrapper around MUX_CLR_SET_UPD that hardcodes the
absent fields, and convert the affected mux definitions in mt8192 and
mt7988 to use it.

Daniel Golle (3):
  clk: mediatek: add MUX_CLR_SET macro
  clk: mediatek: mt8192: use MUX_CLR_SET
  clk: mediatek: mt7988: use MUX_CLR_SET for gate-less muxes

 drivers/clk/mediatek/clk-mt7988-infracfg.c | 80 ++++++++++------------
 drivers/clk/mediatek/clk-mt8192.c          |  4 +-
 drivers/clk/mediatek/clk-mux.h             |  6 ++
 3 files changed, 46 insertions(+), 44 deletions(-)

-- 
2.53.0