From: sboyd@codeaurora•org (Stephen Boyd)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes
Date: Thu, 15 Sep 2016 16:11:32 -0700 [thread overview]
Message-ID: <daee8cd5-c1a1-49c3-e0f8-e83bb9ed3263@codeaurora.org> (raw)
In-Reply-To: <20160915083436.GC10128@lukather>
On 09/15/2016 01:34 AM, Maxime Ripard wrote:
> Hi,
>
> On Thu, Sep 15, 2016 at 02:57:37PM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> Here are 3 fixes for the new sunxi-ng clk driver for sun6i-a31 recently
>> introduced for 4.9. The issues were noticed while working on the display
>> pipeline for the A31/A31s. The second patch follows what Maxime has done
>> for the A33 CCU driver. The third issue was noticed while doing the first
>> patch.
>>
>> I hope we can get this into 4.9 as well, either right in -rc1, or in a
>> later -rc.
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons•com>
>
> Stephen, could you apply those patches directly on top of my previous
> PR, or do you want me to send another one?
>
I can apply directly to clk-next.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-09-15 23:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-15 6:57 [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Chen-Yu Tsai
2016-09-15 6:57 ` [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks Chen-Yu Tsai
2016-09-16 23:04 ` Stephen Boyd
2016-09-15 6:57 ` [PATCH 2/3] clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs Chen-Yu Tsai
2016-09-15 6:57 ` [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk Chen-Yu Tsai
2016-09-16 23:04 ` Stephen Boyd
2016-09-15 8:34 ` [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Maxime Ripard
2016-09-15 23:11 ` Stephen Boyd [this message]
2016-09-18 20:30 ` Maxime Ripard
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