Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

From: <[email-masked]>
Date: Tue, 17 Sep 2019 05:59:18 +0000

On 16.09.2019 22:52, Stephen Boyd wrote:

> Quoting [email-masked] (2019-09-10 23:39:20)
>> From: Eugen Hristev <[email-masked]>
>>
>> The PLL input range needs to be able to allow 24 Mhz crystal as input
>> Update the range accordingly in plla characteristics struct
>>
>> Signed-off-by: Eugen Hristev <[email-masked]>
>> ---
> 
> Is there a Fixes: tag for this? Seems like it was always wrong?
> 

Hi Stephen,

At the initial design , the 12 Mhz was the only possibility for the 
boards themselves. But, with the commit who added this:

Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")

Eugen
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