From: Vignesh Raghavendra <vigneshr@ti•com>
To: <Tudor.Ambarus@microchip•com>, <boris.brezillon@collabora•com>,
<marek.vasut@gmail•com>, <miquel.raynal@bootlin•com>,
<richard@nod•at>, <linux-mtd@lists•infradead.org>
Cc: linux-aspeed@lists•ozlabs.org, andrew@aj•id.au,
linux-kernel@vger•kernel.org, vz@mleia•com,
linux-mediatek@lists•infradead.org, joel@jms•id.au,
matthias.bgg@gmail•com, computersforpeace@gmail•com,
dwmw2@infradead•org, linux-arm-kernel@lists•infradead.org
Subject: Re: [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable()
Date: Thu, 19 Sep 2019 23:04:15 +0530 [thread overview]
Message-ID: <f811a9a6-4b88-e017-5cc6-ad758edbcab3@ti.com> (raw)
In-Reply-To: <20190917155426.7432-20-tudor.ambarus@microchip.com>
On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip•com wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip•com>
>
> Merge:
> spansion_no_read_cr_quad_enable()
> spansion_read_cr_quad_enable()
>
> in spi_nor_sr2_bit1_quad_enable().
>
> Avoid duplication of code by using spi_nor_write_16bit_sr_and_check(),
> the SNOR_F_NO_READ_CR case is treated there.
>
> We now do the Read Back test even for the old
> spansion_no_read_cr_quad_enable() case.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip•com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 89 ++++++++++---------------------------------
> include/linux/mtd/spi-nor.h | 4 +-
> 2 files changed, 22 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 2f79923e7db5..8648666fb9bd 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -907,7 +907,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
> * Write Status (01h) command is available just for the cases
> * in which the QE bit is described in SR2 at BIT(1).
> */
> - sr_cr[1] = CR_QUAD_EN_SPAN;
> + sr_cr[1] = SR2_QUAD_EN_BIT1;
> } else {
> sr_cr[1] = 0;
> }
> @@ -1963,81 +1963,34 @@ static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
> }
>
> /**
> - * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
> + * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
> + * Register 2.
> * @nor: pointer to a 'struct spi_nor'
> *
> - * Set the Quad Enable (QE) bit in the Configuration Register.
> - * This function should be used with QSPI memories not supporting the Read
> - * Configuration Register (35h) instruction.
> - *
> - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
> - * memories.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
> -{
> - u8 *sr_cr = nor->bouncebuf;
> - int ret;
> -
> - /* Keep the current value of the Status Register. */
> - ret = spi_nor_read_sr(nor, &sr_cr[0]);
> - if (ret)
> - return ret;
> -
> - sr_cr[1] = CR_QUAD_EN_SPAN;
> -
> - return spi_nor_write_sr(nor, sr_cr, 2);
> -}
> -
> -/**
> - * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
> - * @nor: pointer to a 'struct spi_nor'
> - *
> - * Set the Quad Enable (QE) bit in the Configuration Register.
> - * This function should be used with QSPI memories supporting the Read
> - * Configuration Register (35h) instruction.
> - *
> - * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
> - * memories.
> + * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
> *
> * Return: 0 on success, -errno otherwise.
> */
> -static int spansion_read_cr_quad_enable(struct spi_nor *nor)
> +static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
> {
> - u8 *sr_cr = nor->bouncebuf;
> int ret;
>
> - /* Check current Quad Enable bit value. */
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> -
> - if (sr_cr[1] & CR_QUAD_EN_SPAN)
> - return 0;
> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> + /* Check current Quad Enable bit value. */
> + ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]);
> + if (ret)
> + return ret;
>
> - sr_cr[1] |= CR_QUAD_EN_SPAN;
> + if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
> + return 0;
> + }
>
> /* Keep the current value of the Status Register. */
> - ret = spi_nor_read_sr(nor, &sr_cr[0]);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_write_sr(nor, sr_cr, 2);
> - if (ret)
> - return ret;
> -
> - /* Read back and check it. */
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> + ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
> if (ret)
> return ret;
>
> - if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
> - dev_err(nor->dev, "Spansion Quad bit not set\n");
> - return -EIO;
> - }
> -
> - return 0;
You need to set QE bit here before writing to CR register. This function
does not do that.
> + return spi_nor_write_16bit_sr_and_check(nor, nor->bouncebuf[0], 0xFF);
Neither does spi_nor_write_16bit_sr_and_check().
We need a function that allows to modify SR2/CR register content as well
so as to set QE bit right?
Regards
Vignesh
> }
>
> /**
> @@ -2117,7 +2070,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
> *
> * Read-modify-write function that clears the Block Protection bits from the
> * Status Register without affecting other bits. The function is tightly
> - * coupled with the spansion_read_cr_quad_enable() function. Both assume that
> + * coupled with the spi_nor_sr2_bit1_quad_enable() function. Both assume that
> * the Write Register with 16 bits, together with the Read Configuration
> * Register (35h) instructions are supported.
> *
> @@ -2138,7 +2091,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
> * When the configuration register Quad Enable bit is one, only the
> * Write Status (01h) command with two data bytes may be used.
> */
> - if (sr_cr[1] & CR_QUAD_EN_SPAN) {
> + if (sr_cr[1] & SR2_QUAD_EN_BIT1) {
> ret = spi_nor_read_sr(nor, &sr_cr[0]);
> if (ret)
> return ret;
> @@ -3642,7 +3595,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * supported.
> */
> nor->flags |= SNOR_F_NO_READ_CR;
> - flash->quad_enable = spansion_no_read_cr_quad_enable;
> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
> break;
>
> case BFPT_DWORD15_QER_SR1_BIT6:
> @@ -3663,7 +3616,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * assumption of a 16-bit Write Status (01h) command.
> */
> nor->flags |= SNOR_F_HAS_16BIT_SR;
> - flash->quad_enable = spansion_read_cr_quad_enable;
> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
> break;
>
> default:
> @@ -4626,7 +4579,7 @@ static void spi_nor_info_init_flash_params(struct spi_nor *nor)
> u8 i, erase_mask;
>
> /* Initialize legacy flash parameters and settings. */
> - flash->quad_enable = spansion_read_cr_quad_enable;
> + flash->quad_enable = spi_nor_sr2_bit1_quad_enable;
> flash->set_4byte = spansion_set_4byte;
> flash->setup = spi_nor_default_setup;
> /* Default to 16-bit Write Status (01h) Command */
> @@ -4844,7 +4797,7 @@ static int spi_nor_init(struct spi_nor *nor)
> int err;
>
> if (nor->clear_sr_bp) {
> - if (nor->flash.quad_enable == spansion_read_cr_quad_enable)
> + if (nor->flash.quad_enable == spi_nor_sr2_bit1_quad_enable)
> nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
>
> err = nor->clear_sr_bp(nor);
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 3a835de90b6a..5590a36eb43e 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -144,10 +144,8 @@
> #define FSR_P_ERR BIT(4) /* Program operation status */
> #define FSR_PT_ERR BIT(1) /* Protection error bit */
>
> -/* Configuration Register bits. */
> -#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
> -
> /* Status Register 2 bits. */
> +#define SR2_QUAD_EN_BIT1 BIT(1)
> #define SR2_QUAD_EN_BIT7 BIT(7)
>
> /* Supported SPI protocols */
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists•infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-09-19 17:36 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 05/23] mtd: spi-nor: Rework read_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 06/23] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 07/23] mtd: spi-nor: Rework read_cr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 10/23] mtd: spi-nor: Rework write_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 14/23] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-09-19 14:33 ` Vignesh Raghavendra
2019-09-19 15:54 ` Tudor.Ambarus
2019-09-20 5:23 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
2019-09-19 17:34 ` Vignesh Raghavendra [this message]
2019-09-20 4:42 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b Tudor.Ambarus
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
2019-09-19 16:07 ` Tudor.Ambarus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f811a9a6-4b88-e017-5cc6-ad758edbcab3@ti.com \
--to=vigneshr@ti$(echo .)com \
--cc=Tudor.Ambarus@microchip$(echo .)com \
--cc=andrew@aj$(echo .)id.au \
--cc=boris.brezillon@collabora$(echo .)com \
--cc=computersforpeace@gmail$(echo .)com \
--cc=dwmw2@infradead$(echo .)org \
--cc=joel@jms$(echo .)id.au \
--cc=linux-arm-kernel@lists$(echo .)infradead.org \
--cc=linux-aspeed@lists$(echo .)ozlabs.org \
--cc=linux-kernel@vger$(echo .)kernel.org \
--cc=linux-mediatek@lists$(echo .)infradead.org \
--cc=linux-mtd@lists$(echo .)infradead.org \
--cc=marek.vasut@gmail$(echo .)com \
--cc=matthias.bgg@gmail$(echo .)com \
--cc=miquel.raynal@bootlin$(echo .)com \
--cc=richard@nod$(echo .)at \
--cc=vz@mleia$(echo .)com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox