Subject: linux-next: manual merge of the drm tree with the drm-intel-fixes tree

From: Stephen Rothwell <[email-masked]>
Date: Mon, 28 Oct 2013 16:46:09 +1100

Hi Dave,

Today's linux-next merge of the drm tree got a conflict in
drivers/gpu/drm/i915/intel_dp.c between commit 0cc4b69960f3 ("drm/i915:
Mask LPSP to get PSR working even with Power Well in use by audio") from
Linus' tree and commit 52e1e223456e ("drm/i915/dp: workaround BIOS eDP
bpp clamping issue") from the drm-intel-fixes tree and commits
18442d087864 ("drm/i915: Fix port_clock and adjusted_mode.clock readout
all over") and 18b5992c3756 ("drm/i915: Calculate PSR register offsets
from base + gen") from the drm tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    [email-masked]

diff --cc drivers/gpu/drm/i915/intel_dp.c
index 1a431377d83b,1e3d2720d811..000000000000
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -1402,31 -1469,20 +1469,40 @@@ static void intel_dp_get_config(struct 
  			pipe_config->port_clock = 270000;
  	}
  
 +	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 +	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
 +		/*
 +		 * This is a big fat ugly hack.
 +		 *
 +		 * Some machines in UEFI boot mode provide us a VBT that has 18
 +		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
 +		 * unknown we fail to light up. Yet the same BIOS boots up with
 +		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
 +		 * max, not what it tells us to use.
 +		 *
 +		 * Note: This will still be broken if the eDP panel is not lit
 +		 * up by the BIOS, and thus we can't get the mode at module
 +		 * load.
 +		 */
 +		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
 +			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
 +		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
 +	}
++
+ 	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
+ 					    &pipe_config->dp_m_n);
+ 
+ 	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
+ 		ironlake_check_encoder_dotclock(pipe_config, dotclock);
+ 
+ 	pipe_config->adjusted_mode.crtc_clock = dotclock;
  }
  
- static bool is_edp_psr(struct intel_dp *intel_dp)
+ static bool is_edp_psr(struct drm_device *dev)
  {
- 	return is_edp(intel_dp) &&
- 		intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
+ 	struct drm_i915_private *dev_priv = dev->dev_private;
+ 
+ 	return dev_priv->psr.sink_support;
  }
  
  static bool intel_edp_is_psr_enabled(struct drm_device *dev)
@@@ -1486,8 -1542,8 +1562,8 @@@ static void intel_edp_psr_setup(struct 
  	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
  
  	/* Avoid continuous PSR exit by masking memup and hpd */
 -	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
 +	I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
- 		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
+ 		   EDP_PSR_DEBUG_MASK_HPD);
  
  	intel_dp->psr_setup_done = true;
  }