Subject: linux-next: manual merge of the kvm-ppc tree with the kvm tree

From: Stephen Rothwell <[email-masked]>
Date: Mon, 4 Aug 2014 18:04:03 +1000

Hi Alexander,

Today's linux-next merge of the kvm-ppc tree got a conflict in
Documentation/virtual/kvm/api.txt between commit bf5590f37919 ("KVM:
Reformat KVM_SET_ONE_REG register documentation") from the kvm tree and
commit a0840240c0c6 ("KVM: PPC: Book3S: Fix LPCR one_reg interface")
from the kvm-ppc tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    [email-masked]

diff --cc Documentation/virtual/kvm/api.txt
index 68cda1fc3d52,a21ff2265c21..000000000000
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@@ -1797,151 -1777,123 +1800,152 @@@ and architecture specific registers. Ea
  and their own constants and width. To keep track of the implemented
  registers, find a list below:
  
 -  Arch  |       Register        | Width (bits)
 -        |                       |
 -  PPC   | KVM_REG_PPC_HIOR      | 64
 -  PPC   | KVM_REG_PPC_IAC1      | 64
 -  PPC   | KVM_REG_PPC_IAC2      | 64
 -  PPC   | KVM_REG_PPC_IAC3      | 64
 -  PPC   | KVM_REG_PPC_IAC4      | 64
 -  PPC   | KVM_REG_PPC_DAC1      | 64
 -  PPC   | KVM_REG_PPC_DAC2      | 64
 -  PPC   | KVM_REG_PPC_DABR      | 64
 -  PPC   | KVM_REG_PPC_DSCR      | 64
 -  PPC   | KVM_REG_PPC_PURR      | 64
 -  PPC   | KVM_REG_PPC_SPURR     | 64
 -  PPC   | KVM_REG_PPC_DAR       | 64
 -  PPC   | KVM_REG_PPC_DSISR     | 32
 -  PPC   | KVM_REG_PPC_AMR       | 64
 -  PPC   | KVM_REG_PPC_UAMOR     | 64
 -  PPC   | KVM_REG_PPC_MMCR0     | 64
 -  PPC   | KVM_REG_PPC_MMCR1     | 64
 -  PPC   | KVM_REG_PPC_MMCRA     | 64
 -  PPC   | KVM_REG_PPC_MMCR2     | 64
 -  PPC   | KVM_REG_PPC_MMCRS     | 64
 -  PPC   | KVM_REG_PPC_SIAR      | 64
 -  PPC   | KVM_REG_PPC_SDAR      | 64
 -  PPC   | KVM_REG_PPC_SIER      | 64
 -  PPC   | KVM_REG_PPC_PMC1      | 32
 -  PPC   | KVM_REG_PPC_PMC2      | 32
 -  PPC   | KVM_REG_PPC_PMC3      | 32
 -  PPC   | KVM_REG_PPC_PMC4      | 32
 -  PPC   | KVM_REG_PPC_PMC5      | 32
 -  PPC   | KVM_REG_PPC_PMC6      | 32
 -  PPC   | KVM_REG_PPC_PMC7      | 32
 -  PPC   | KVM_REG_PPC_PMC8      | 32
 -  PPC   | KVM_REG_PPC_FPR0      | 64
 +  Arch  |           Register            | Width (bits)
 +        |                               |
 +  PPC   | KVM_REG_PPC_HIOR              | 64
 +  PPC   | KVM_REG_PPC_IAC1              | 64
 +  PPC   | KVM_REG_PPC_IAC2              | 64
 +  PPC   | KVM_REG_PPC_IAC3              | 64
 +  PPC   | KVM_REG_PPC_IAC4              | 64
 +  PPC   | KVM_REG_PPC_DAC1              | 64
 +  PPC   | KVM_REG_PPC_DAC2              | 64
 +  PPC   | KVM_REG_PPC_DABR              | 64
 +  PPC   | KVM_REG_PPC_DSCR              | 64
 +  PPC   | KVM_REG_PPC_PURR              | 64
 +  PPC   | KVM_REG_PPC_SPURR             | 64
 +  PPC   | KVM_REG_PPC_DAR               | 64
 +  PPC   | KVM_REG_PPC_DSISR             | 32
 +  PPC   | KVM_REG_PPC_AMR               | 64
 +  PPC   | KVM_REG_PPC_UAMOR             | 64
 +  PPC   | KVM_REG_PPC_MMCR0             | 64
 +  PPC   | KVM_REG_PPC_MMCR1             | 64
 +  PPC   | KVM_REG_PPC_MMCRA             | 64
 +  PPC   | KVM_REG_PPC_MMCR2             | 64
 +  PPC   | KVM_REG_PPC_MMCRS             | 64
 +  PPC   | KVM_REG_PPC_SIAR              | 64
 +  PPC   | KVM_REG_PPC_SDAR              | 64
 +  PPC   | KVM_REG_PPC_SIER              | 64
 +  PPC   | KVM_REG_PPC_PMC1              | 32
 +  PPC   | KVM_REG_PPC_PMC2              | 32
 +  PPC   | KVM_REG_PPC_PMC3              | 32
 +  PPC   | KVM_REG_PPC_PMC4              | 32
 +  PPC   | KVM_REG_PPC_PMC5              | 32
 +  PPC   | KVM_REG_PPC_PMC6              | 32
 +  PPC   | KVM_REG_PPC_PMC7              | 32
 +  PPC   | KVM_REG_PPC_PMC8              | 32
 +  PPC   | KVM_REG_PPC_FPR0              | 64
 +          ...
 +  PPC   | KVM_REG_PPC_FPR31             | 64
 +  PPC   | KVM_REG_PPC_VR0               | 128
            ...
 -  PPC   | KVM_REG_PPC_FPR31     | 64
 -  PPC   | KVM_REG_PPC_VR0       | 128
 +  PPC   | KVM_REG_PPC_VR31              | 128
 +  PPC   | KVM_REG_PPC_VSR0              | 128
            ...
 -  PPC   | KVM_REG_PPC_VR31      | 128
 -  PPC   | KVM_REG_PPC_VSR0      | 128
 +  PPC   | KVM_REG_PPC_VSR31             | 128
 +  PPC   | KVM_REG_PPC_FPSCR             | 64
 +  PPC   | KVM_REG_PPC_VSCR              | 32
 +  PPC   | KVM_REG_PPC_VPA_ADDR          | 64
 +  PPC   | KVM_REG_PPC_VPA_SLB           | 128
 +  PPC   | KVM_REG_PPC_VPA_DTL           | 128
 +  PPC   | KVM_REG_PPC_EPCR              | 32
 +  PPC   | KVM_REG_PPC_EPR               | 32
 +  PPC   | KVM_REG_PPC_TCR               | 32
 +  PPC   | KVM_REG_PPC_TSR               | 32
 +  PPC   | KVM_REG_PPC_OR_TSR            | 32
 +  PPC   | KVM_REG_PPC_CLEAR_TSR         | 32
 +  PPC   | KVM_REG_PPC_MAS0              | 32
 +  PPC   | KVM_REG_PPC_MAS1              | 32
 +  PPC   | KVM_REG_PPC_MAS2              | 64
 +  PPC   | KVM_REG_PPC_MAS7_3            | 64
 +  PPC   | KVM_REG_PPC_MAS4              | 32
 +  PPC   | KVM_REG_PPC_MAS6              | 32
 +  PPC   | KVM_REG_PPC_MMUCFG            | 32
 +  PPC   | KVM_REG_PPC_TLB0CFG           | 32
 +  PPC   | KVM_REG_PPC_TLB1CFG           | 32
 +  PPC   | KVM_REG_PPC_TLB2CFG           | 32
 +  PPC   | KVM_REG_PPC_TLB3CFG           | 32
 +  PPC   | KVM_REG_PPC_TLB0PS            | 32
 +  PPC   | KVM_REG_PPC_TLB1PS            | 32
 +  PPC   | KVM_REG_PPC_TLB2PS            | 32
 +  PPC   | KVM_REG_PPC_TLB3PS            | 32
 +  PPC   | KVM_REG_PPC_EPTCFG            | 32
 +  PPC   | KVM_REG_PPC_ICP_STATE         | 64
 +  PPC   | KVM_REG_PPC_TB_OFFSET         | 64
 +  PPC   | KVM_REG_PPC_SPMC1             | 32
 +  PPC   | KVM_REG_PPC_SPMC2             | 32
 +  PPC   | KVM_REG_PPC_IAMR              | 64
 +  PPC   | KVM_REG_PPC_TFHAR             | 64
 +  PPC   | KVM_REG_PPC_TFIAR             | 64
 +  PPC   | KVM_REG_PPC_TEXASR            | 64
 +  PPC   | KVM_REG_PPC_FSCR              | 64
 +  PPC   | KVM_REG_PPC_PSPB              | 32
 +  PPC   | KVM_REG_PPC_EBBHR             | 64
 +  PPC   | KVM_REG_PPC_EBBRR             | 64
 +  PPC   | KVM_REG_PPC_BESCR             | 64
 +  PPC   | KVM_REG_PPC_TAR               | 64
 +  PPC   | KVM_REG_PPC_DPDES             | 64
 +  PPC   | KVM_REG_PPC_DAWR              | 64
 +  PPC   | KVM_REG_PPC_DAWRX             | 64
 +  PPC   | KVM_REG_PPC_CIABR             | 64
 +  PPC   | KVM_REG_PPC_IC                | 64
 +  PPC   | KVM_REG_PPC_VTB               | 64
 +  PPC   | KVM_REG_PPC_CSIGR             | 64
 +  PPC   | KVM_REG_PPC_TACR              | 64
 +  PPC   | KVM_REG_PPC_TCSCR             | 64
 +  PPC   | KVM_REG_PPC_PID               | 64
 +  PPC   | KVM_REG_PPC_ACOP              | 64
 +  PPC   | KVM_REG_PPC_VRSAVE            | 32
 +  PPC   | KVM_REG_PPC_LPCR              | 64
++  PPC   | KVM_REG_PPC_LPCR_64		| 64
 +  PPC   | KVM_REG_PPC_PPR               | 64
 +  PPC   | KVM_REG_PPC_ARCH_COMPAT       | 32
 +  PPC   | KVM_REG_PPC_DABRX             | 32
 +  PPC   | KVM_REG_PPC_WORT              | 64
 +  PPC   | KVM_REG_PPC_TM_GPR0           | 64
            ...
 -  PPC   | KVM_REG_PPC_VSR31     | 128
 -  PPC   | KVM_REG_PPC_FPSCR     | 64
 -  PPC   | KVM_REG_PPC_VSCR      | 32
 -  PPC   | KVM_REG_PPC_VPA_ADDR  | 64
 -  PPC   | KVM_REG_PPC_VPA_SLB   | 128
 -  PPC   | KVM_REG_PPC_VPA_DTL   | 128
 -  PPC   | KVM_REG_PPC_EPCR	| 32
 -  PPC   | KVM_REG_PPC_EPR	| 32
 -  PPC   | KVM_REG_PPC_TCR	| 32
 -  PPC   | KVM_REG_PPC_TSR	| 32
 -  PPC   | KVM_REG_PPC_OR_TSR	| 32
 -  PPC   | KVM_REG_PPC_CLEAR_TSR	| 32
 -  PPC   | KVM_REG_PPC_MAS0	| 32
 -  PPC   | KVM_REG_PPC_MAS1	| 32
 -  PPC   | KVM_REG_PPC_MAS2	| 64
 -  PPC   | KVM_REG_PPC_MAS7_3	| 64
 -  PPC   | KVM_REG_PPC_MAS4	| 32
 -  PPC   | KVM_REG_PPC_MAS6	| 32
 -  PPC   | KVM_REG_PPC_MMUCFG	| 32
 -  PPC   | KVM_REG_PPC_TLB0CFG	| 32
 -  PPC   | KVM_REG_PPC_TLB1CFG	| 32
 -  PPC   | KVM_REG_PPC_TLB2CFG	| 32
 -  PPC   | KVM_REG_PPC_TLB3CFG	| 32
 -  PPC   | KVM_REG_PPC_TLB0PS	| 32
 -  PPC   | KVM_REG_PPC_TLB1PS	| 32
 -  PPC   | KVM_REG_PPC_TLB2PS	| 32
 -  PPC   | KVM_REG_PPC_TLB3PS	| 32
 -  PPC   | KVM_REG_PPC_EPTCFG	| 32
 -  PPC   | KVM_REG_PPC_ICP_STATE | 64
 -  PPC   | KVM_REG_PPC_TB_OFFSET	| 64
 -  PPC   | KVM_REG_PPC_SPMC1	| 32
 -  PPC   | KVM_REG_PPC_SPMC2	| 32
 -  PPC   | KVM_REG_PPC_IAMR	| 64
 -  PPC   | KVM_REG_PPC_TFHAR	| 64
 -  PPC   | KVM_REG_PPC_TFIAR	| 64
 -  PPC   | KVM_REG_PPC_TEXASR	| 64
 -  PPC   | KVM_REG_PPC_FSCR	| 64
 -  PPC   | KVM_REG_PPC_PSPB	| 32
 -  PPC   | KVM_REG_PPC_EBBHR	| 64
 -  PPC   | KVM_REG_PPC_EBBRR	| 64
 -  PPC   | KVM_REG_PPC_BESCR	| 64
 -  PPC   | KVM_REG_PPC_TAR	| 64
 -  PPC   | KVM_REG_PPC_DPDES	| 64
 -  PPC   | KVM_REG_PPC_DAWR	| 64
 -  PPC   | KVM_REG_PPC_DAWRX	| 64
 -  PPC   | KVM_REG_PPC_CIABR	| 64
 -  PPC   | KVM_REG_PPC_IC	| 64
 -  PPC   | KVM_REG_PPC_VTB	| 64
 -  PPC   | KVM_REG_PPC_CSIGR	| 64
 -  PPC   | KVM_REG_PPC_TACR	| 64
 -  PPC   | KVM_REG_PPC_TCSCR	| 64
 -  PPC   | KVM_REG_PPC_PID	| 64
 -  PPC   | KVM_REG_PPC_ACOP	| 64
 -  PPC   | KVM_REG_PPC_VRSAVE	| 32
 -  PPC   | KVM_REG_PPC_LPCR	| 32
 -  PPC   | KVM_REG_PPC_LPCR_64	| 64
 -  PPC   | KVM_REG_PPC_PPR	| 64
 -  PPC   | KVM_REG_PPC_ARCH_COMPAT 32
 -  PPC   | KVM_REG_PPC_DABRX     | 32
 -  PPC   | KVM_REG_PPC_WORT      | 64
 -  PPC   | KVM_REG_PPC_TM_GPR0	| 64
 +  PPC   | KVM_REG_PPC_TM_GPR31          | 64
 +  PPC   | KVM_REG_PPC_TM_VSR0           | 128
            ...
 -  PPC   | KVM_REG_PPC_TM_GPR31	| 64
 -  PPC   | KVM_REG_PPC_TM_VSR0	| 128
 +  PPC   | KVM_REG_PPC_TM_VSR63          | 128
 +  PPC   | KVM_REG_PPC_TM_CR             | 64
 +  PPC   | KVM_REG_PPC_TM_LR             | 64
 +  PPC   | KVM_REG_PPC_TM_CTR            | 64
 +  PPC   | KVM_REG_PPC_TM_FPSCR          | 64
 +  PPC   | KVM_REG_PPC_TM_AMR            | 64
 +  PPC   | KVM_REG_PPC_TM_PPR            | 64
 +  PPC   | KVM_REG_PPC_TM_VRSAVE         | 64
 +  PPC   | KVM_REG_PPC_TM_VSCR           | 32
 +  PPC   | KVM_REG_PPC_TM_DSCR           | 64
 +  PPC   | KVM_REG_PPC_TM_TAR            | 64
 +        |                               |
 +  MIPS  | KVM_REG_MIPS_R0               | 64
            ...
 -  PPC   | KVM_REG_PPC_TM_VSR63	| 128
 -  PPC   | KVM_REG_PPC_TM_CR	| 64
 -  PPC   | KVM_REG_PPC_TM_LR	| 64
 -  PPC   | KVM_REG_PPC_TM_CTR	| 64
 -  PPC   | KVM_REG_PPC_TM_FPSCR	| 64
 -  PPC   | KVM_REG_PPC_TM_AMR	| 64
 -  PPC   | KVM_REG_PPC_TM_PPR	| 64
 -  PPC   | KVM_REG_PPC_TM_VRSAVE	| 64
 -  PPC   | KVM_REG_PPC_TM_VSCR	| 32
 -  PPC   | KVM_REG_PPC_TM_DSCR	| 64
 -  PPC   | KVM_REG_PPC_TM_TAR	| 64
 +  MIPS  | KVM_REG_MIPS_R31              | 64
 +  MIPS  | KVM_REG_MIPS_HI               | 64
 +  MIPS  | KVM_REG_MIPS_LO               | 64
 +  MIPS  | KVM_REG_MIPS_PC               | 64
 +  MIPS  | KVM_REG_MIPS_CP0_INDEX        | 32
 +  MIPS  | KVM_REG_MIPS_CP0_CONTEXT      | 64
 +  MIPS  | KVM_REG_MIPS_CP0_USERLOCAL    | 64
 +  MIPS  | KVM_REG_MIPS_CP0_PAGEMASK     | 32
 +  MIPS  | KVM_REG_MIPS_CP0_WIRED        | 32
 +  MIPS  | KVM_REG_MIPS_CP0_HWRENA       | 32
 +  MIPS  | KVM_REG_MIPS_CP0_BADVADDR     | 64
 +  MIPS  | KVM_REG_MIPS_CP0_COUNT        | 32
 +  MIPS  | KVM_REG_MIPS_CP0_ENTRYHI      | 64
 +  MIPS  | KVM_REG_MIPS_CP0_COMPARE      | 32
 +  MIPS  | KVM_REG_MIPS_CP0_STATUS       | 32
 +  MIPS  | KVM_REG_MIPS_CP0_CAUSE        | 32
 +  MIPS  | KVM_REG_MIPS_CP0_EPC          | 64
 +  MIPS  | KVM_REG_MIPS_CP0_CONFIG       | 32
 +  MIPS  | KVM_REG_MIPS_CP0_CONFIG1      | 32
 +  MIPS  | KVM_REG_MIPS_CP0_CONFIG2      | 32
 +  MIPS  | KVM_REG_MIPS_CP0_CONFIG3      | 32
 +  MIPS  | KVM_REG_MIPS_CP0_CONFIG7      | 32
 +  MIPS  | KVM_REG_MIPS_CP0_ERROREPC     | 64
 +  MIPS  | KVM_REG_MIPS_COUNT_CTL        | 64
 +  MIPS  | KVM_REG_MIPS_COUNT_RESUME     | 64
 +  MIPS  | KVM_REG_MIPS_COUNT_HZ         | 64
  
  ARM registers are mapped using the lower 32 bits.  The upper 16 of that
  is the register group type, or coprocessor number:
@@@ -2931,13 -2867,12 +2935,13 @@@ The fields in each entry are defined a
           this function/index combination

- 6. Capabilities that can be enabled
- -----------------------------------
+ 6. Capabilities that can be enabled on vCPUs
+ --------------------------------------------
  
 -There are certain capabilities that change the behavior of the virtual CPU when
 -enabled. To enable them, please see section 4.37. Below you can find a list of
 -capabilities and what their effect on the vCPU is when enabling them.
 +There are certain capabilities that change the behavior of the virtual CPU or
 +the virtual machine when enabled. To enable them, please see section 4.37.
 +Below you can find a list of capabilities and what their effect on the vCPU or
 +the virtual machine is when enabling them.
  
  The following information is provided along with the description:
  
@@@ -3083,11 -3007,43 +3087,51 @@@ Parameters: args[0] is the XICS device 
  
  This capability connects the vcpu to an in-kernel XICS device.
  
 +6.8 KVM_CAP_S390_IRQCHIP
 +
 +Architectures: s390
 +Target: vm
 +Parameters: none
 +
 +This capability enables the in-kernel irqchip for s390. Please refer to
 +"4.24 KVM_CREATE_IRQCHIP" for details.
+ 
+ 7. Capabilities that can be enabled on VMs
+ ------------------------------------------
+ 
+ There are certain capabilities that change the behavior of the virtual
+ machine when enabled. To enable them, please see section 4.37. Below
+ you can find a list of capabilities and what their effect on the VM
+ is when enabling them.
+ 
+ The following information is provided along with the description:
+ 
+   Architectures: which instruction set architectures provide this ioctl.
+       x86 includes both i386 and x86_64.
+ 
+   Parameters: what parameters are accepted by the capability.
+ 
+   Returns: the return value.  General error numbers (EBADF, ENOMEM, EINVAL)
+       are not detailed, but errors with specific meanings are.
+ 
+ 
+ 7.1 KVM_CAP_PPC_ENABLE_HCALL
+ 
+ Architectures: ppc
+ Parameters: args[0] is the sPAPR hcall number
+ 	    args[1] is 0 to disable, 1 to enable in-kernel handling
+ 
+ This capability controls whether individual sPAPR hypercalls (hcalls)
+ get handled by the kernel or not.  Enabling or disabling in-kernel
+ handling of an hcall is effective across the VM.  On creation, an
+ initial set of hcalls are enabled for in-kernel handling, which
+ consists of those hcalls for which in-kernel handlers were implemented
+ before this capability was implemented.  If disabled, the kernel will
+ not to attempt to handle the hcall, but will always exit to userspace
+ to handle it.  Note that it may not make sense to enable some and
+ disable others of a group of related hcalls, but KVM does not prevent
+ userspace from doing that.
+ 
+ If the hcall number specified is not one that has an in-kernel
+ implementation, the KVM_ENABLE_CAP ioctl will fail with an EINVAL
+ error.