Subject: linux-next: manual merge of the crypto tree with the arm-soc tree

From: Mark Brown <[email-masked]>
Date: Sun, 15 Sep 2019 21:55:02 +0100

Hi all,

Today's linux-next merge of the crypto tree got a conflict in:

  arch/arm64/boot/dts/freescale/imx8mq.dtsi

between commit:

  a99b26b14bea506 ("arm64: dts: imx8mq: Add MIPI D-PHY")

from the arm-soc tree and commit:

  007b3cf0af8cb7d ("arm64: dts: imx8mq: Add CAAM node")

from the crypto tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts (generally DTS updates go through arm-soc).

diff --cc arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 046a0c8c8dd56,752d5a61878cb..0000000000000
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@@ -743,19 -728,36 +743,49 @@@
  				status = "disabled";
  			};
  
 +			dphy: dphy@30a00300 {
 +				compatible = "fsl,imx8mq-mipi-dphy";
 +				reg = <0x30a00300 0x100>;
 +				clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 +				clock-names = "phy_ref";
 +				assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 +				assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 +				assigned-clock-rates = <24000000>;
 +				#phy-cells = <0>;
 +				power-domains = <&pgc_mipi>;
 +				status = "disabled";
 +			};
 +
+ 			crypto: crypto@30900000 {
+ 				compatible = "fsl,sec-v4.0";
+ 				#address-cells = <1>;
+ 				#size-cells = <1>;
+ 				reg = <0x30900000 0x40000>;
+ 				ranges = <0 0x30900000 0x40000>;
+ 				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ 				clocks = <&clk IMX8MQ_CLK_AHB>,
+ 					 <&clk IMX8MQ_CLK_IPG_ROOT>;
+ 				clock-names = "aclk", "ipg";
+ 
+ 				sec_jr0: jr@1000 {
+ 					compatible = "fsl,sec-v4.0-job-ring";
+ 					reg = <0x1000 0x1000>;
+ 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ 				};
+ 
+ 				sec_jr1: jr@2000 {
+ 					compatible = "fsl,sec-v4.0-job-ring";
+ 					reg = <0x2000 0x1000>;
+ 					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ 				};
+ 
+ 				sec_jr2: jr@3000 {
+ 					compatible = "fsl,sec-v4.0-job-ring";
+ 					reg = <0x3000 0x1000>;
+ 					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ 				};
+ 			};
+ 
  			i2c1: i2c@30a20000 {
  				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
  				reg = <0x30a20000 0x10000>;