Subject: linux-next: manual merge of the clk tree with the imx-mxs tree

From: Stephen Rothwell <[email-masked]>
Date: Fri, 18 Oct 2019 09:20:56 +1100

Hi all,

Today's linux-next merge of the clk tree got a conflict in:

  drivers/clk/imx/clk-imx8mn.c

between commit:

  0ae4fbc63c31 ("clk: imx8mn: Use common 1443X/1416X PLL clock structure")

from the imx-mxs tree and commit:

  727e12cde9f6 ("clk: imx: imx8mn: drop unused pll enum")

from the clk tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/clk/imx/clk-imx8mn.c
index 7a5590b967d5,ccd05321f043..000000000000
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@@ -25,20 -25,75 +25,6 @@@ static u32 share_count_disp
  static u32 share_count_pdm;
  static u32 share_count_nand;
  
- enum {
- 	ARM_PLL,
- 	GPU_PLL,
- 	VPU_PLL,
- 	SYS_PLL1,
- 	SYS_PLL2,
- 	SYS_PLL3,
- 	DRAM_PLL,
- 	AUDIO_PLL1,
- 	AUDIO_PLL2,
- 	VIDEO_PLL2,
- 	NR_PLLS,
 -static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
 -	PLL_1416X_RATE(1800000000U, 225, 3, 0),
 -	PLL_1416X_RATE(1600000000U, 200, 3, 0),
 -	PLL_1416X_RATE(1500000000U, 375, 3, 1),
 -	PLL_1416X_RATE(1400000000U, 350, 3, 1),
 -	PLL_1416X_RATE(1200000000U, 300, 3, 1),
 -	PLL_1416X_RATE(1000000000U, 250, 3, 1),
 -	PLL_1416X_RATE(800000000U,  200, 3, 1),
 -	PLL_1416X_RATE(750000000U,  250, 2, 2),
 -	PLL_1416X_RATE(700000000U,  350, 3, 2),
 -	PLL_1416X_RATE(600000000U,  300, 3, 2),
 -};
 -
 -static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
 -	PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
 -	PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
 -};
 -
 -static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
 -	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
 -	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
 -};
 -
 -static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
 -	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
 -};
 -
 -static struct imx_pll14xx_clk imx8mn_audio_pll = {
 -		.type = PLL_1443X,
 -		.rate_table = imx8mn_audiopll_tbl,
 -		.rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
 -};
 -
 -static struct imx_pll14xx_clk imx8mn_video_pll = {
 -		.type = PLL_1443X,
 -		.rate_table = imx8mn_videopll_tbl,
 -		.rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
 -};
 -
 -static struct imx_pll14xx_clk imx8mn_dram_pll = {
 -		.type = PLL_1443X,
 -		.rate_table = imx8mn_drampll_tbl,
 -		.rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
 -};
 -
 -static struct imx_pll14xx_clk imx8mn_arm_pll = {
 -		.type = PLL_1416X,
 -		.rate_table = imx8mn_pll1416x_tbl,
 -		.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
 -};
 -
 -static struct imx_pll14xx_clk imx8mn_gpu_pll = {
 -		.type = PLL_1416X,
 -		.rate_table = imx8mn_pll1416x_tbl,
 -		.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
 -};
 -
 -static struct imx_pll14xx_clk imx8mn_vpu_pll = {
 -		.type = PLL_1416X,
 -		.rate_table = imx8mn_pll1416x_tbl,
 -		.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
 -};
 -
 -static struct imx_pll14xx_clk imx8mn_sys_pll = {
 -		.type = PLL_1416X,
 -		.rate_table = imx8mn_pll1416x_tbl,
 -		.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
--};
--
  static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
  static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
  static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };