Subject: Coverity: dcn20_cap_soc_clocks(): UNINTENDED_INTEGER_DIVISION

From: coverity-bot <[email-masked]>
Date: Mon, 4 Nov 2019 09:42:40 -0800

Hello!

This is an experimental automated report about issues detected by Coverity
from a scan of next-20191031 as part of the linux-next weekly scan project:
https://scan.coverity.com/projects/linux-next-weekly-scan

You're getting this email because you were associated with the identified
lines of code (noted below) that were touched by recent commits:

7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource")

Coverity reported the following:

*** CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3048 in dcn20_cap_soc_clocks()
3042     		struct pp_smu_nv_clock_table max_clocks)
3043     {
3044     	int i;
3045
3046     	// First pass - cap all clocks higher than the reported max
3047     	for (i = 0; i < bb->num_states; i++) {
vvv     CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
vvv     Dividing integer expressions "max_clocks.dcfClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored.
3048     		if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3049     				&& max_clocks.dcfClockInKhz != 0)
3050     			bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3051
3052     		if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3053     						&& max_clocks.uClockInKhz != 0)
/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3056 in dcn20_cap_soc_clocks()
3050     			bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3051
3052     		if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3053     						&& max_clocks.uClockInKhz != 0)
3054     			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3055
vvv     CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
vvv     Dividing integer expressions "max_clocks.fabricClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored.
3056     		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3057     						&& max_clocks.fabricClockInKhz != 0)
3058     			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3059
3060     		if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3061     						&& max_clocks.displayClockInKhz != 0)
/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3060 in dcn20_cap_soc_clocks()
3054     			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3055
3056     		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3057     						&& max_clocks.fabricClockInKhz != 0)
3058     			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3059
vvv     CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
vvv     Dividing integer expressions "max_clocks.displayClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored.
3060     		if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3061     						&& max_clocks.displayClockInKhz != 0)
3062     			bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3063
3064     		if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3065     						&& max_clocks.dppClockInKhz != 0)
/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3068 in dcn20_cap_soc_clocks()
3062     			bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3063
3064     		if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3065     						&& max_clocks.dppClockInKhz != 0)
3066     			bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3067
vvv     CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
vvv     Dividing integer expressions "max_clocks.phyClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored.
3068     		if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3069     						&& max_clocks.phyClockInKhz != 0)
3070     			bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3071
3072     		if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3073     						&& max_clocks.socClockInKhz != 0)
/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3072 in dcn20_cap_soc_clocks()
3066     			bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3067
3068     		if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3069     						&& max_clocks.phyClockInKhz != 0)
3070     			bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3071
vvv     CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
vvv     Dividing integer expressions "max_clocks.socClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored.
3072     		if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3073     						&& max_clocks.socClockInKhz != 0)
3074     			bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3075
3076     		if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3077     						&& max_clocks.dscClockInKhz != 0)
/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3076 in dcn20_cap_soc_clocks()
3070     			bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3071
3072     		if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3073     						&& max_clocks.socClockInKhz != 0)
3074     			bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3075
vvv     CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
vvv     Dividing integer expressions "max_clocks.dscClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored.
3076     		if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3077     						&& max_clocks.dscClockInKhz != 0)
3078     			bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3079     	}
3080
3081     	// Second pass - remove all duplicate clock states
/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c: 3064 in dcn20_cap_soc_clocks()
3058     			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3059
3060     		if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3061     						&& max_clocks.displayClockInKhz != 0)
3062     			bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3063
vvv     CID 1487393:    (UNINTENDED_INTEGER_DIVISION)
vvv     Dividing integer expressions "max_clocks.dppClockInKhz" and "1000U", and then converting the integer quotient to type "double". Any remainder, or fractional part of the quotient, is ignored.
3064     		if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3065     						&& max_clocks.dppClockInKhz != 0)
3066     			bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3067
3068     		if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3069     						&& max_clocks.phyClockInKhz != 0)

If this is a false positive, please let us know so we can mark it as
such, or teach the Coverity rules to be smarter. If not, please make
sure fixes get into linux-next. :) For patches fixing this, please
include these lines (but double-check the "Fixes" first):

Reported-by: coverity-bot <[email-masked]>
Addresses-Coverity-ID: 1487393 ("UNINTENDED_INTEGER_DIVISION")
Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource")

Thanks for your attention!

-- 
Coverity-bot