Subject: linux-next: manual merge of the drivers-x86 tree with the tip tree

From: Stephen Rothwell <[email-masked]>
Date: Thu, 26 Mar 2020 15:05:23 +1100

Hi all,

Today's linux-next merge of the drivers-x86 tree got a conflict in:

  drivers/platform/x86/intel_pmc_core.c

between commit:

  a69b3b1d4cf0 ("platform/x86: Convert to new CPU match macros")

from the tip tree and commit:

  16292bed9c56 ("platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support")

from the drivers-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/platform/x86/intel_pmc_core.c
index 3df33ff50faa,d265cd5b1f45..000000000000
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@@ -871,18 -1144,19 +1144,19 @@@ static inline void pmc_core_dbgfs_unreg
  #endif /* CONFIG_DEBUG_FS */
  
  static const struct x86_cpu_id intel_pmc_core_ids[] = {
 -	INTEL_CPU_FAM6(SKYLAKE_L, spt_reg_map),
 -	INTEL_CPU_FAM6(SKYLAKE, spt_reg_map),
 -	INTEL_CPU_FAM6(KABYLAKE_L, spt_reg_map),
 -	INTEL_CPU_FAM6(KABYLAKE, spt_reg_map),
 -	INTEL_CPU_FAM6(CANNONLAKE_L, cnp_reg_map),
 -	INTEL_CPU_FAM6(ICELAKE_L, icl_reg_map),
 -	INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map),
 -	INTEL_CPU_FAM6(COMETLAKE, cnp_reg_map),
 -	INTEL_CPU_FAM6(COMETLAKE_L, cnp_reg_map),
 -	INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
 -	INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
 -	INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map),
 -	INTEL_CPU_FAM6(ATOM_TREMONT_L, tgl_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,		&spt_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,		&spt_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,		&spt_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,		&spt_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L,	&cnp_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		&icl_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI,	&icl_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,		&cnp_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,		&cnp_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		&tgl_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&tgl_reg_map),
 +	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	&tgl_reg_map),
++	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&tgl_reg_map),
  	{}
  };