Subject: linux-next: manual merge of the drm tree with Linus' tree

From: Stephen Rothwell <[email-masked]>
Date: Thu, 1 Dec 2022 09:57:00 +1100

Hi all,

Today's linux-next merge of the drm tree got a conflict in:

  drivers/gpu/drm/i915/gt/intel_gt.c

between commit:

  04aa64375f48 ("drm/i915: fix TLB invalidation for Gen12 video and compute engines")

from Linus' tree and commit:

  46c507f03a46 ("drm/i915/gt: Always use MCR functions on multicast registers")

from the drm tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/gt/intel_gt.c
index 7caa3412a244,0325f071046c..000000000000
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@@ -1018,16 -1103,17 +1108,22 @@@ static void mmio_invalidate_full(struc
  		if (!intel_engine_pm_is_awake(engine))
  			continue;
  
- 		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
- 		if (!i915_mmio_reg_offset(rb.reg))
- 			continue;
- 
- 		if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
- 		    engine->class == VIDEO_ENHANCEMENT_CLASS ||
- 		    engine->class == COMPUTE_CLASS))
- 			rb.bit = _MASKED_BIT_ENABLE(rb.bit);
- 
- 		intel_uncore_write_fw(uncore, rb.reg, rb.bit);
+ 		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ 			intel_gt_mcr_multicast_write_fw(gt,
+ 							xehp_regs[engine->class],
+ 							BIT(engine->instance));
+ 		} else {
+ 			rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
+ 			if (!i915_mmio_reg_offset(rb.reg))
+ 				continue;
+ 
++			if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
++			    engine->class == VIDEO_ENHANCEMENT_CLASS ||
++			    engine->class == COMPUTE_CLASS))
++				rb.bit = _MASKED_BIT_ENABLE(rb.bit);
++
+ 			intel_uncore_write_fw(uncore, rb.reg, rb.bit);
+ 		}
  		awake |= engine->mask;
  	}