Subject: linux-next: manual merge of the drm-intel tree with the drm tree

From: Stephen Rothwell <[email-masked]>
Date: Tue, 30 May 2023 11:57:52 +1000

Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in:

  drivers/gpu/drm/i915/i915_pci.c

between commit:

  5e352e32aec2 ("drm/i915: preparation for using PAT index")

from the drm tree and commits:

  5af5169d7582 ("drm/i915: Convert INTEL_INFO()->display to a pointer")
  18e0deeed8c8 ("drm/i915/display: Move display runtime info to display structure")

from the drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/i915/i915_pci.c
index 75cbccd1a441,34bc732a6375..000000000000
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -27,9 -27,9 +27,10 @@@
  #include <drm/i915_pciids.h>
  
  #include "display/intel_display.h"
+ #include "display/intel_display_driver.h"
  #include "gt/intel_gt_regs.h"
  #include "gt/intel_sa_media.h"
 +#include "gem/i915_gem_object_types.h"
  
  #include "i915_driver.h"
  #include "i915_drv.h"
@@@ -40,162 -40,8 +41,40 @@@
  #define PLATFORM(x) .platform = (x)
  #define GEN(x) \
  	.__runtime.graphics.ip.ver = (x), \
- 	.__runtime.media.ip.ver = (x), \
- 	.__runtime.display.ip.ver = (x)
- 
- #define NO_DISPLAY .__runtime.pipe_mask = 0
- 
- #define I845_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 	}
- 
- #define I9XX_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 	}
- 
- #define IVB_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = PIPE_C_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- 	}
- 
- #define HSW_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = PIPE_C_OFFSET, \
- 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
- 	}
- 
- #define CHV_PIPE_OFFSETS \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET, \
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
- 	}
- 
- #define I845_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 	}
- 
- #define I9XX_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = CURSOR_B_OFFSET, \
- 	}
- 
- #define CHV_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = CURSOR_B_OFFSET, \
- 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
- 	}
- 
- #define IVB_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
- 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
- 	}
- 
- #define TGL_CURSOR_OFFSETS \
- 	.display.cursor_offsets = { \
- 		[PIPE_A] = CURSOR_A_OFFSET, \
- 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
- 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
- 		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
- 	}
- 
- #define I845_COLORS \
- 	.display.color = { .gamma_lut_size = 256 }
- #define I9XX_COLORS \
- 	.display.color = { .gamma_lut_size = 129, \
- 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 	}
- #define ILK_COLORS \
- 	.display.color = { .gamma_lut_size = 1024 }
- #define IVB_COLORS \
- 	.display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
- #define CHV_COLORS \
- 	.display.color = { \
- 		.degamma_lut_size = 65, .gamma_lut_size = 257, \
- 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 	}
- #define GLK_COLORS \
- 	.display.color = { \
- 		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
- 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
- 	}
- #define ICL_COLORS \
- 	.display.color = { \
- 		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
- 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
- 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- 	}
+ 	.__runtime.media.ip.ver = (x)
  
 +#define LEGACY_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 0, \
 +		[I915_CACHE_LLC]    = 1, \
 +		[I915_CACHE_L3_LLC] = 2, \
 +		[I915_CACHE_WT]     = 3, \
 +	}
 +
 +#define TGL_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 3, \
 +		[I915_CACHE_LLC]    = 0, \
 +		[I915_CACHE_L3_LLC] = 0, \
 +		[I915_CACHE_WT]     = 2, \
 +	}
 +
 +#define PVC_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 0, \
 +		[I915_CACHE_LLC]    = 3, \
 +		[I915_CACHE_L3_LLC] = 3, \
 +		[I915_CACHE_WT]     = 2, \
 +	}
 +
 +#define MTL_CACHELEVEL \
 +	.cachelevel_to_pat = { \
 +		[I915_CACHE_NONE]   = 2, \
 +		[I915_CACHE_LLC]    = 3, \
 +		[I915_CACHE_L3_LLC] = 3, \
 +		[I915_CACHE_WT]     = 1, \
 +	}
 +
  /* Keep in gen based order, and chronological order within a gen */
  
  #define GEN_DEFAULT_PAGE_SIZES \
@@@ -221,13 -61,8 +94,10 @@@
  	.has_snoop = true, \
  	.has_coherent_ggtt = false, \
  	.dma_mask_size = 32, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	I9XX_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  #define I845_FEATURES \
  	GEN(2), \
@@@ -244,13 -74,8 +109,10 @@@
  	.has_snoop = true, \
  	.has_coherent_ggtt = false, \
  	.dma_mask_size = 32, \
 +	.max_pat_index = 3, \
- 	I845_PIPE_OFFSETS, \
- 	I845_CURSOR_OFFSETS, \
- 	I845_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info i830_info = {
  	I830_FEATURES,
@@@ -285,13 -105,8 +142,10 @@@ static const struct intel_device_info i
  	.has_snoop = true, \
  	.has_coherent_ggtt = true, \
  	.dma_mask_size = 32, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	I9XX_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info i915g_info = {
  	GEN3_FEATURES,
@@@ -379,13 -166,8 +205,10 @@@ static const struct intel_device_info p
  	.has_snoop = true, \
  	.has_coherent_ggtt = true, \
  	.dma_mask_size = 36, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	I9XX_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info i965g_info = {
  	GEN4_FEATURES,
@@@ -435,13 -208,8 +249,10 @@@ static const struct intel_device_info g
  	/* ilk does support rc6, but we do not implement [power] contexts */ \
  	.has_rc6 = 0, \
  	.dma_mask_size = 36, \
 +	.max_pat_index = 3, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	ILK_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info ilk_d_info = {
  	GEN5_FEATURES,
@@@ -471,15 -234,10 +277,12 @@@ static const struct intel_device_info i
  	.has_rc6p = 0, \
  	.has_rps = true, \
  	.dma_mask_size = 40, \
 +	.max_pat_index = 3, \
  	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
  	.__runtime.ppgtt_size = 31, \
- 	I9XX_PIPE_OFFSETS, \
- 	I9XX_CURSOR_OFFSETS, \
- 	ILK_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  #define SNB_D_PLATFORM \
  	GEN6_FEATURES, \
@@@ -526,15 -280,10 +325,12 @@@ static const struct intel_device_info s
  	.has_reset_engine = true, \
  	.has_rps = true, \
  	.dma_mask_size = 40, \
 +	.max_pat_index = 3, \
  	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
  	.__runtime.ppgtt_size = 31, \
- 	IVB_PIPE_OFFSETS, \
- 	IVB_CURSOR_OFFSETS, \
- 	IVB_COLORS, \
  	GEN_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  #define IVB_D_PLATFORM \
  	GEN7_FEATURES, \
@@@ -585,22 -331,14 +378,16 @@@ static const struct intel_device_info v
  	.has_rc6 = 1,
  	.has_reset_engine = true,
  	.has_rps = true,
- 	.display.has_gmch = 1,
- 	.display.has_hotplug = 1,
  	.dma_mask_size = 40,
 +	.max_pat_index = 3,
  	.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
  	.__runtime.ppgtt_size = 31,
  	.has_snoop = true,
  	.has_coherent_ggtt = false,
  	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
- 	.display.mmio_offset = VLV_DISPLAY_BASE,
- 	I9XX_PIPE_OFFSETS,
- 	I9XX_CURSOR_OFFSETS,
- 	I9XX_COLORS,
  	GEN_DEFAULT_PAGE_SIZES,
  	GEN_DEFAULT_REGIONS,
 +	LEGACY_CACHELEVEL,
  };
  
  #define G75_FEATURES  \
@@@ -686,21 -415,14 +464,16 @@@ static const struct intel_device_info c
  	.has_rc6 = 1,
  	.has_rps = true,
  	.has_logical_ring_contexts = 1,
- 	.display.has_gmch = 1,
  	.dma_mask_size = 39,
 +	.max_pat_index = 3,
  	.__runtime.ppgtt_type = INTEL_PPGTT_FULL,
  	.__runtime.ppgtt_size = 32,
  	.has_reset_engine = 1,
  	.has_snoop = true,
  	.has_coherent_ggtt = false,
- 	.display.mmio_offset = VLV_DISPLAY_BASE,
- 	CHV_PIPE_OFFSETS,
- 	CHV_CURSOR_OFFSETS,
- 	CHV_COLORS,
  	GEN_DEFAULT_PAGE_SIZES,
  	GEN_DEFAULT_REGIONS,
 +	LEGACY_CACHELEVEL,
  };
  
  #define GEN9_DEFAULT_PAGE_SIZES \
@@@ -781,14 -482,8 +533,10 @@@ static const struct intel_device_info s
  	.has_reset_engine = 1, \
  	.has_snoop = true, \
  	.has_coherent_ggtt = false, \
- 	.display.has_ipc = 1, \
 +	.max_pat_index = 3, \
- 	HSW_PIPE_OFFSETS, \
- 	IVB_CURSOR_OFFSETS, \
- 	IVB_COLORS, \
  	GEN9_DEFAULT_PAGE_SIZES, \
 -	GEN_DEFAULT_REGIONS
 +	GEN_DEFAULT_REGIONS, \
 +	LEGACY_CACHELEVEL
  
  static const struct intel_device_info bxt_info = {
  	GEN9_LP_FEATURES,
@@@ -920,33 -587,8 +640,9 @@@ static const struct intel_device_info j
  #define GEN12_FEATURES \
  	GEN11_FEATURES, \
  	GEN(12), \
- 	.display.abox_mask = GENMASK(2, 1), \
- 	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- 	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
- 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- 	.display.pipe_offsets = { \
- 		[TRANSCODER_A] = PIPE_A_OFFSET, \
- 		[TRANSCODER_B] = PIPE_B_OFFSET, \
- 		[TRANSCODER_C] = PIPE_C_OFFSET, \
- 		[TRANSCODER_D] = PIPE_D_OFFSET, \
- 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
- 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
- 	}, \
- 	.display.trans_offsets = { \
- 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- 		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
- 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
- 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- 	}, \
- 	TGL_CURSOR_OFFSETS, \
- 	TGL_CACHELEVEL, \
++	.max_pat_index = 3 \
  	.has_global_mocs = 1, \
- 	.has_pxp = 1, \
- 	.display.has_dsb = 1, \
- 	.max_pat_index = 3
+ 	.has_pxp = 1
  
  static const struct intel_device_info tgl_info = {
  	GEN12_FEATURES,
@@@ -1162,24 -739,14 +795,16 @@@ static const struct intel_device_info p
  	.__runtime.graphics.ip.rel = 60,
  	.__runtime.media.ip.rel = 60,
  	PLATFORM(INTEL_PONTEVECCHIO),
- 	NO_DISPLAY,
  	.has_flat_ccs = 0,
 +	.max_pat_index = 7,
  	.__runtime.platform_engine_mask =
  		BIT(BCS0) |
  		BIT(VCS0) |
  		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
  	.require_force_probe = 1,
 +	PVC_CACHELEVEL,
  };
  
- #define XE_LPDP_FEATURES	\
- 	XE_LPD_FEATURES,	\
- 	.__runtime.display.ip.ver = 14,	\
- 	.display.has_cdclk_crawl = 1, \
- 	.display.has_cdclk_squash = 1, \
- 	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
- 
  static const struct intel_gt_definition xelpmp_extra_gt[] = {
  	{
  		.type = GT_MEDIA,