Subject: Re: linux-next: manual merge of the kvm-riscv tree with the risc-v tree

From: Stephen Rothwell <[email-masked]>
Date: Mon, 3 Jul 2023 10:54:22 +1000

Hi all,

On Mon, 19 Jun 2023 12:33:00 +1000 Stephen Rothwell <[email-masked]> wrote:
>
> Today's linux-next merge of the kvm-riscv tree got a conflict in:
> 
>   arch/riscv/include/uapi/asm/kvm.h
> 
> between commit:
> 
>   0f4b82579716 ("riscv: KVM: Add vector lazy save/restore support")
> 
> from the risc-v tree and commits:
> 
>   00f918f61c56 ("RISC-V: KVM: Skeletal in-kernel AIA irqchip support")
>   89d01306e34d ("RISC-V: KVM: Implement device interface for AIA irqchip")
>   289a007b98b0 ("RISC-V: KVM: Expose APLIC registers as attributes of AIA irqchip")
>   4fe9eadad83b ("RISC-V: KVM: Expose IMSIC registers as attributes of AIA irqchip")
> 
> from the kvm-riscv tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> 
> diff --cc arch/riscv/include/uapi/asm/kvm.h
> index 855c047e86d4,61d7fecc4899..000000000000
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@@ -204,13 -204,77 +205,84 @@@ enum KVM_RISCV_SBI_EXT_ID 
>   #define KVM_REG_RISCV_SBI_MULTI_REG_LAST	\
>   		KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
>   
>  +/* V extension registers are mapped as type 9 */
>  +#define KVM_REG_RISCV_VECTOR		(0x09 << KVM_REG_RISCV_TYPE_SHIFT)
>  +#define KVM_REG_RISCV_VECTOR_CSR_REG(name)	\
>  +		(offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
>  +#define KVM_REG_RISCV_VECTOR_REG(n)	\
>  +		((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
>  +
> + /* Device Control API: RISC-V AIA */
> + #define KVM_DEV_RISCV_APLIC_ALIGN		0x1000
> + #define KVM_DEV_RISCV_APLIC_SIZE		0x4000
> + #define KVM_DEV_RISCV_APLIC_MAX_HARTS		0x4000
> + #define KVM_DEV_RISCV_IMSIC_ALIGN		0x1000
> + #define KVM_DEV_RISCV_IMSIC_SIZE		0x1000
> + 
> + #define KVM_DEV_RISCV_AIA_GRP_CONFIG		0
> + #define KVM_DEV_RISCV_AIA_CONFIG_MODE		0
> + #define KVM_DEV_RISCV_AIA_CONFIG_IDS		1
> + #define KVM_DEV_RISCV_AIA_CONFIG_SRCS		2
> + #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS	3
> + #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT	4
> + #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS	5
> + #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS	6
> + 
> + /*
> +  * Modes of RISC-V AIA device:
> +  * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
> +  * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
> +  * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
> +  *    available otherwise fallback to trap-n-emulation
> +  */
> + #define KVM_DEV_RISCV_AIA_MODE_EMUL		0
> + #define KVM_DEV_RISCV_AIA_MODE_HWACCEL		1
> + #define KVM_DEV_RISCV_AIA_MODE_AUTO		2
> + 
> + #define KVM_DEV_RISCV_AIA_IDS_MIN		63
> + #define KVM_DEV_RISCV_AIA_IDS_MAX		2048
> + #define KVM_DEV_RISCV_AIA_SRCS_MAX		1024
> + #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX	8
> + #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN	24
> + #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX	56
> + #define KVM_DEV_RISCV_AIA_HART_BITS_MAX		16
> + #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX	8
> + 
> + #define KVM_DEV_RISCV_AIA_GRP_ADDR		1
> + #define KVM_DEV_RISCV_AIA_ADDR_APLIC		0
> + #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu)	(1 + (__vcpu))
> + #define KVM_DEV_RISCV_AIA_ADDR_MAX		\
> + 		(1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
> + 
> + #define KVM_DEV_RISCV_AIA_GRP_CTRL		2
> + #define KVM_DEV_RISCV_AIA_CTRL_INIT		0
> + 
> + /*
> +  * The device attribute type contains the memory mapped offset of the
> +  * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
> +  */
> + #define KVM_DEV_RISCV_AIA_GRP_APLIC		3
> + 
> + /*
> +  * The lower 12-bits of the device attribute type contains the iselect
> +  * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
> +  * bits contains the VCPU id.
> +  */
> + #define KVM_DEV_RISCV_AIA_GRP_IMSIC		4
> + #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS	12
> + #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK	\
> + 		((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
> + #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel)	\
> + 		(((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
> + 		 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
> + #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr)	\
> + 		((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
> + #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr)	\
> + 		((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
> + 
> + /* One single KVM irqchip, ie. the AIA */
> + #define KVM_NR_IRQCHIPS			1
> + 
>   #endif
>   
>   #endif /* __LINUX_KVM_RISCV_H */

This is now a conflict between the kvm tree and Linus' tree.

-- 
Cheers,
Stephen Rothwell