From: Stephen Rothwell <sfr@canb•auug.org.au>
To: Jason Gunthorpe <jgg@nvidia•com>, Joerg Roedel <joro@8bytes•org>
Cc: Jason Gunthorpe <jgg@ziepe•ca>,
Jiapeng Chong <jiapeng.chong@linux•alibaba.com>,
Joao Martins <joao.m.martins@oracle•com>,
Joerg Roedel <jroedel@suse•de>,
Linux Kernel Mailing List <linux-kernel@vger•kernel.org>,
Linux Next Mailing List <linux-next@vger•kernel.org>,
Lu Baolu <baolu.lu@linux•intel.com>
Subject: linux-next: manual merge of the iommufd tree with the iommu tree
Date: Mon, 23 Oct 2023 15:56:06 +1100 [thread overview]
Message-ID: <20231023155606.247fa998@canb.auug.org.au> (raw)
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Hi all,
Today's linux-next merge of the iommufd tree got a conflict in:
drivers/iommu/intel/pasid.c
between commit:
c61c255e114c ("iommu/vt-d: Remove unused function")
from the iommu tree and commit:
3c576c995219 ("iommu/intel: Access/Dirty bit support for SL domains")
from the iommufd tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/iommu/intel/pasid.c
index 06ddb3c927f5,b9264b9174e8..000000000000
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@@ -335,6 -340,45 +340,36 @@@ static inline void pasid_set_fault_enab
pasid_set_bits(&pe->val[0], 1 << 1, 0);
}
+ /*
+ * Enable second level A/D bits by setting the SLADE (Second Level
+ * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
+ * entry.
+ */
+ static inline void pasid_set_ssade(struct pasid_entry *pe)
+ {
+ pasid_set_bits(&pe->val[0], 1 << 9, 1 << 9);
+ }
+
+ /*
+ * Disable second level A/D bits by clearing the SLADE (Second Level
+ * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
+ * entry.
+ */
+ static inline void pasid_clear_ssade(struct pasid_entry *pe)
+ {
+ pasid_set_bits(&pe->val[0], 1 << 9, 0);
+ }
+
+ /*
+ * Checks if second level A/D bits specifically the SLADE (Second Level
+ * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
+ * entry is set.
+ */
+ static inline bool pasid_get_ssade(struct pasid_entry *pe)
+ {
+ return pasid_get_bits(&pe->val[0]) & (1 << 9);
+ }
+
-/*
- * Setup the WPE(Write Protect Enable) field (Bit 132) of a
- * scalable mode PASID entry.
- */
-static inline void pasid_set_wpe(struct pasid_entry *pe)
-{
- pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4);
-}
-
/*
* Setup the P(Present) field (Bit 0) of a scalable mode PASID
* entry.
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next reply other threads:[~2023-10-23 4:56 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 4:56 Stephen Rothwell [this message]
-- strict thread matches above, loose matches on Subject: below --
2025-06-30 6:00 linux-next: manual merge of the iommufd tree with the iommu tree Stephen Rothwell
2025-06-30 13:02 ` Jason Gunthorpe
2025-03-21 8:09 Stephen Rothwell
2023-10-27 4:55 Stephen Rothwell
2023-10-27 6:15 ` Stephen Rothwell
2023-10-30 18:26 ` Jason Gunthorpe
2023-10-31 5:12 ` Stephen Rothwell
2023-10-31 11:31 ` Jason Gunthorpe
2023-11-02 23:53 ` Stephen Rothwell
2023-11-03 0:33 ` Jason Gunthorpe
2023-10-26 3:27 Stephen Rothwell
2023-10-25 4:44 Stephen Rothwell
2023-10-25 12:17 ` Jason Gunthorpe
2023-11-02 23:53 ` Stephen Rothwell
2023-10-25 4:34 Stephen Rothwell
2023-10-25 12:12 ` Jason Gunthorpe
2023-10-25 12:16 ` Baolu Lu
2023-10-25 12:17 ` Jason Gunthorpe
2023-10-25 12:25 ` Baolu Lu
2023-10-11 5:03 Stephen Rothwell
2023-10-11 13:58 ` Jason Gunthorpe
2023-08-16 6:21 Stephen Rothwell
2022-11-04 4:24 Stephen Rothwell
2022-11-04 12:33 ` Jason Gunthorpe
2022-11-04 19:21 ` Jason Gunthorpe
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