Subject: linux-next: manual merge of the tip tree with the stm32 tree

From: Stephen Rothwell <[email-masked]>
Date: Fri, 26 Apr 2024 13:35:35 +1000

Hi all,

Today's linux-next merge of the tip tree got a conflict in:

  arch/arm64/boot/dts/st/stm32mp251.dtsi

between commit:

  2886ab7437de ("arm64: dts: st: add rcc support for STM32MP25")

from the stm32 tree and commit:

  fbc3facb0b5c ("arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251")

from the tip tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/arm64/boot/dts/st/stm32mp251.dtsi
index 4b48e4ed2d28,e7d1614dc744..000000000000
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@@ -356,93 -168,99 +356,186 @@@
  			};
  		};
  
 +		rcc: clock-controller@44200000 {
 +			compatible = "st,stm32mp25-rcc";
 +			reg = <0x44200000 0x10000>;
 +			#clock-cells = <1>;
 +			#reset-cells = <1>;
 +			clocks = <&scmi_clk CK_SCMI_HSE>,
 +				<&scmi_clk CK_SCMI_HSI>,
 +				<&scmi_clk CK_SCMI_MSI>,
 +				<&scmi_clk CK_SCMI_LSE>,
 +				<&scmi_clk CK_SCMI_LSI>,
 +				<&scmi_clk CK_SCMI_HSE_DIV2>,
 +				<&scmi_clk CK_SCMI_ICN_HS_MCU>,
 +				<&scmi_clk CK_SCMI_ICN_LS_MCU>,
 +				<&scmi_clk CK_SCMI_ICN_SDMMC>,
 +				<&scmi_clk CK_SCMI_ICN_DDR>,
 +				<&scmi_clk CK_SCMI_ICN_DISPLAY>,
 +				<&scmi_clk CK_SCMI_ICN_HSL>,
 +				<&scmi_clk CK_SCMI_ICN_NIC>,
 +				<&scmi_clk CK_SCMI_ICN_VID>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_07>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_08>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_09>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_10>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_11>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_12>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_13>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_14>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_15>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_16>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_17>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_18>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_19>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_20>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_21>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_22>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_23>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_24>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_25>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_26>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_27>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_28>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_29>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_30>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_31>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_32>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_33>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_34>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_35>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_36>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_37>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_38>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_39>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_40>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_41>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_42>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_43>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_44>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_45>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_46>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_47>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_48>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_49>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_50>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_51>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_52>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_53>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_54>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_55>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_56>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_57>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_58>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_59>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_60>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_61>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_62>,
 +				<&scmi_clk CK_SCMI_FLEXGEN_63>,
 +				<&scmi_clk CK_SCMI_ICN_APB1>,
 +				<&scmi_clk CK_SCMI_ICN_APB2>,
 +				<&scmi_clk CK_SCMI_ICN_APB3>,
 +				<&scmi_clk CK_SCMI_ICN_APB4>,
 +				<&scmi_clk CK_SCMI_ICN_APBDBG>,
 +				<&scmi_clk CK_SCMI_TIMG1>,
 +				<&scmi_clk CK_SCMI_TIMG2>,
 +				<&scmi_clk CK_SCMI_PLL3>,
 +				<&clk_dsi_txbyte>;
 +		};
 +
+ 		exti1: interrupt-controller@44220000 {
+ 			compatible = "st,stm32mp1-exti", "syscon";
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+ 			reg = <0x44220000 0x400>;
+ 			interrupts-extended =
+ 				<&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_0 */
+ 				<&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_10 */
+ 				<&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 1   IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ 				<0>,						/* EXTI_20 */
+ 				<&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_30 */
+ 				<&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ 				<0>,
+ 				<&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_40 */
+ 				<&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_50 */
+ 				<0>,
+ 				<0>,
+ 				<0>,
+ 				<0>,
+ 				<0>,
+ 				<0>,
+ 				<0>,
+ 				<0>,
+ 				<&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ 				<0>,						/* EXTI_60 */
+ 				<&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ 				<0>,
+ 				<0>,
+ 				<&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ 				<0>,
+ 				<0>,
+ 				<&intc GIC_SPI 10  IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ 				<0>,
+ 				<&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_70 */
+ 				<0>,
+ 				<&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ 				<0>,						/* EXTI_80 */
+ 				<0>,
+ 				<0>,
+ 				<&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ 				<&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
+ 
  		syscfg: syscon@44230000 {
  			compatible = "st,stm32mp25-syscfg", "syscon";
  			reg = <0x44230000 0x10000>;