From: Stephen Rothwell <sfr@canb•auug.org.au>
To: Thomas Gleixner <tglx@linutronix•de>,
Ingo Molnar <mingo@redhat•com>, "H. Peter Anvin" <hpa@zytor•com>,
Peter Zijlstra <peterz@infradead•org>,
"Rafael J. Wysocki" <rjw@rjwysocki•net>
Cc: "Borislav Petkov (AMD)" <bp@alien8•de>,
Linux Kernel Mailing List <linux-kernel@vger•kernel.org>,
Linux Next Mailing List <linux-next@vger•kernel.org>,
Mario Limonciello <mario.limonciello@amd•com>,
Perry Yuan <perry.yuan@amd•com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel•com>,
Srinivas Pandruvada <srinivas.pandruvada@linux•intel.com>,
Xiaojian Du <Xiaojian.Du@amd•com>
Subject: Re: linux-next: manual merge of the tip tree with the pm tree
Date: Wed, 17 Jul 2024 11:41:55 +1000 [thread overview]
Message-ID: <20240717114155.1a3d4c07@canb.auug.org.au> (raw)
In-Reply-To: <20240702141555.3494c5a6@canb.auug.org.au>
[-- Attachment #1: Type: text/plain, Size: 16376 bytes --]
Hi all,
On Tue, 2 Jul 2024 14:15:55 +1000 Stephen Rothwell <sfr@canb•auug.org.au> wrote:
>
> Today's linux-next merge of the tip tree got a conflict in:
>
> arch/x86/include/asm/cpufeatures.h
>
> between commits:
>
> c7107750b2ff ("x86/cpufeatures: Add AMD FAST CPPC feature flag")
> 7ea81936b853 ("x86/cpufeatures: Add HWP highest perf change feature flag")
>
> from the pm tree and commit:
>
> 78ce84b9e0a5 ("x86/cpufeatures: Flip the /proc/cpuinfo appearance logic")
>
> from the tip tree.
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging. You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
>
> --
> Cheers,
> Stephen Rothwell
>
> diff --cc arch/x86/include/asm/cpufeatures.h
> index 0d99515530d3,6007462e03d6..000000000000
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@@ -283,90 -283,89 +283,90 @@@
> *
> * Reuse free bits when adding new feature flags!
> */
> - #define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
> - #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
> - #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
> - #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
> - #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
> - #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
> - #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
> - #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
> - #define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */
> - #define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */
> - #define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */
> - #define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */
> - #define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
> - #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
> - #define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */
> - #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
> - #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
> - #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
> - #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
> - #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
> - #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
> - #define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */
> - #define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */
> - #define X86_FEATURE_USER_SHSTK (11*32+23) /* Shadow stack support for user mode applications */
> - #define X86_FEATURE_SRSO (11*32+24) /* "" AMD BTB untrain RETs */
> - #define X86_FEATURE_SRSO_ALIAS (11*32+25) /* "" AMD BTB untrain RETs through aliasing */
> - #define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* "" Issue an IBPB only on VMEXIT */
> - #define X86_FEATURE_APIC_MSRS_FENCE (11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
> - #define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */
> - #define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */
> - #define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */
> - #define X86_FEATURE_ZEN1 (11*32+31) /* "" CPU based on Zen1 microarchitecture */
> + #define X86_FEATURE_CQM_LLC (11*32+ 0) /* "cqm_llc" LLC QoS if 1 */
> + #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* "cqm_occup_llc" LLC occupancy monitoring */
> + #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* "cqm_mbm_total" LLC Total MBM monitoring */
> + #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* "cqm_mbm_local" LLC Local MBM monitoring */
> + #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* LFENCE in user entry SWAPGS path */
> + #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* LFENCE in kernel entry SWAPGS path */
> + #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* "split_lock_detect" #AC for split lock */
> + #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* Per-thread Memory Bandwidth Allocation */
> + #define X86_FEATURE_SGX1 (11*32+ 8) /* Basic SGX */
> + #define X86_FEATURE_SGX2 (11*32+ 9) /* SGX Enclave Dynamic Memory Management (EDMM) */
> + #define X86_FEATURE_ENTRY_IBPB (11*32+10) /* Issue an IBPB on kernel entry */
> + #define X86_FEATURE_RRSBA_CTRL (11*32+11) /* RET prediction control */
> + #define X86_FEATURE_RETPOLINE (11*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */
> + #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* Use LFENCE for Spectre variant 2 */
> + #define X86_FEATURE_RETHUNK (11*32+14) /* Use REturn THUNK */
> + #define X86_FEATURE_UNRET (11*32+15) /* AMD BTB untrain return */
> + #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* Use IBPB during runtime firmware calls */
> + #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* Fill RSB on VM exit when EIBRS is enabled */
> + #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* SGX EDECCSSA user leaf function */
> + #define X86_FEATURE_CALL_DEPTH (11*32+19) /* Call depth tracking for RSB stuffing */
> + #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* MSR IA32_TSX_CTRL (Intel) implemented */
> + #define X86_FEATURE_SMBA (11*32+21) /* Slow Memory Bandwidth Allocation */
> + #define X86_FEATURE_BMEC (11*32+22) /* Bandwidth Monitoring Event Configuration */
> + #define X86_FEATURE_USER_SHSTK (11*32+23) /* "user_shstk" Shadow stack support for user mode applications */
> + #define X86_FEATURE_SRSO (11*32+24) /* AMD BTB untrain RETs */
> + #define X86_FEATURE_SRSO_ALIAS (11*32+25) /* AMD BTB untrain RETs through aliasing */
> + #define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* Issue an IBPB only on VMEXIT */
> + #define X86_FEATURE_APIC_MSRS_FENCE (11*32+27) /* IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
> + #define X86_FEATURE_ZEN2 (11*32+28) /* CPU based on Zen2 microarchitecture */
> + #define X86_FEATURE_ZEN3 (11*32+29) /* CPU based on Zen3 microarchitecture */
> + #define X86_FEATURE_ZEN4 (11*32+30) /* CPU based on Zen4 microarchitecture */
> + #define X86_FEATURE_ZEN1 (11*32+31) /* CPU based on Zen1 microarchitecture */
>
> /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> - #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
> - #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
> - #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */
> - #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */
> - #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
> - #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
> - #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
> - #define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */
> - #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
> - #define X86_FEATURE_WRMSRNS (12*32+19) /* "" Non-serializing WRMSR */
> - #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
> - #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
> - #define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */
> + #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
> + #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
> + #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */
> + #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* Intel Architectural PerfMon Extension */
> + #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
> + #define X86_FEATURE_FSRS (12*32+11) /* Fast short REP STOSB */
> + #define X86_FEATURE_FSRC (12*32+12) /* Fast short REP {CMPSB,SCASB} */
> + #define X86_FEATURE_FRED (12*32+17) /* "fred" Flexible Return and Event Delivery */
> + #define X86_FEATURE_LKGS (12*32+18) /* Load "kernel" (userspace) GS */
> + #define X86_FEATURE_WRMSRNS (12*32+19) /* Non-serializing WRMSR */
> + #define X86_FEATURE_AMX_FP16 (12*32+21) /* AMX fp16 Support */
> + #define X86_FEATURE_AVX_IFMA (12*32+23) /* Support for VPMADD52[H,L]UQ */
> + #define X86_FEATURE_LAM (12*32+26) /* "lam" Linear Address Masking */
>
> /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
> - #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
> - #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
> - #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
> - #define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */
> - #define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
> - #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
> - #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
> - #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
> - #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
> - #define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */
> - #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
> - #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
> - #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
> - #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
> - #define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */
> - #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
> - #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
> + #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */
> + #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */
> + #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
> + #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */
> + #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
> + #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
> + #define X86_FEATURE_AMD_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
> + #define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
> + #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
> + #define X86_FEATURE_AMD_PPIN (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
> + #define X86_FEATURE_AMD_SSBD (13*32+24) /* Speculative Store Bypass Disable */
> + #define X86_FEATURE_VIRT_SSBD (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
> + #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* Speculative Store Bypass is fixed in hardware. */
> + #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */
> + #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
> + #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */
> + #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */
>
> /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
> - #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
> - #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
> - #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
> - #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
> - #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
> - #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
> - #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
> - #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
> - #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
> - #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
> - #define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* "" HWP Highest perf change */
> - #define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */
> + #define X86_FEATURE_DTHERM (14*32+ 0) /* "dtherm" Digital Thermal Sensor */
> + #define X86_FEATURE_IDA (14*32+ 1) /* "ida" Intel Dynamic Acceleration */
> + #define X86_FEATURE_ARAT (14*32+ 2) /* "arat" Always Running APIC Timer */
> + #define X86_FEATURE_PLN (14*32+ 4) /* "pln" Intel Power Limit Notification */
> + #define X86_FEATURE_PTS (14*32+ 6) /* "pts" Intel Package Thermal Status */
> + #define X86_FEATURE_HWP (14*32+ 7) /* "hwp" Intel Hardware P-states */
> + #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* "hwp_notify" HWP Notification */
> + #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* "hwp_act_window" HWP Activity Window */
> + #define X86_FEATURE_HWP_EPP (14*32+10) /* "hwp_epp" HWP Energy Perf. Preference */
> + #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* "hwp_pkg_req" HWP Package Level Request */
> ++#define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* HWP Highest perf change */
> + #define X86_FEATURE_HFI (14*32+19) /* "hfi" Hardware Feedback Interface */
>
> /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
> - #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
> - #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
> + #define X86_FEATURE_NPT (15*32+ 0) /* "npt" Nested Page Table support */
> + #define X86_FEATURE_LBRV (15*32+ 1) /* "lbrv" LBR Virtualization support */
> #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
> #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
> #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
> @@@ -466,12 -466,11 +467,12 @@@
> *
> * Reuse free bits when adding new feature flags!
> */
> - #define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */
> - #define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */
> - #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */
> - #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */
> - #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */
> - #define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */
> + #define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* "amd_lbr_pmc_freeze" AMD LBR and PMC Freeze */
> + #define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* Clear branch history at syscall entry using SW loop */
> + #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */
> + #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */
> + #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
> ++#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */
>
> /*
> * BUG word(s)
This is now a conflict between the pm tree and Linus' tree.
--
Cheers,
Stephen Rothwell
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next prev parent reply other threads:[~2024-07-17 1:42 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-02 4:15 linux-next: manual merge of the tip tree with the pm tree Stephen Rothwell
2024-07-02 9:25 ` Borislav Petkov
2024-07-17 1:41 ` Stephen Rothwell [this message]
2024-07-17 2:33 ` srinivas pandruvada
2024-07-17 9:49 ` Borislav Petkov
-- strict thread matches above, loose matches on Subject: below --
2026-06-03 13:32 Mark Brown
2026-06-04 12:33 ` Frederic Weisbecker
2026-05-25 14:16 Mark Brown
2026-02-04 13:52 Mark Brown
2026-02-04 14:48 ` Wysocki, Rafael J
2026-02-04 14:56 ` Sebastian Andrzej Siewior
2025-05-16 6:15 Stephen Rothwell
2025-05-16 7:54 ` Ingo Molnar
2025-05-16 9:54 ` Stephen Rothwell
2025-05-16 12:45 ` Ingo Molnar
2025-05-28 3:52 ` Stephen Rothwell
2025-05-12 4:55 Stephen Rothwell
2025-05-12 5:23 ` Stephen Rothwell
2025-05-12 20:45 ` Mario Limonciello
2025-05-15 15:49 ` Ingo Molnar
2025-05-15 15:50 ` Mario Limonciello
2025-05-28 3:50 ` Stephen Rothwell
2025-05-28 14:14 ` Limonciello, Mario
2025-05-28 22:12 ` Stephen Rothwell
2025-05-01 3:58 Stephen Rothwell
2025-05-06 15:07 ` Wysocki, Rafael J
2025-05-06 17:43 ` Ingo Molnar
2025-04-17 3:43 Stephen Rothwell
2025-04-17 11:22 ` Ingo Molnar
2024-06-24 17:06 Mark Brown
2024-06-25 3:00 ` Xiaojian Du
2024-06-25 4:25 ` Borislav Petkov
2024-06-25 4:51 ` Xiaojian Du
2021-02-17 5:07 Stephen Rothwell
2021-02-17 10:15 ` Andy Shevchenko
2021-02-22 0:34 ` Stephen Rothwell
2018-10-08 2:44 Stephen Rothwell
2018-10-08 10:06 ` Rafael J. Wysocki
2018-10-08 10:34 ` Andy Shevchenko
2018-10-08 2:40 Stephen Rothwell
2018-10-08 10:05 ` Rafael J. Wysocki
2018-10-08 10:41 ` Andy Shevchenko
2018-03-23 2:20 Stephen Rothwell
2018-03-23 6:09 ` Ingo Molnar
2018-03-23 21:09 ` Rafael J. Wysocki
2018-03-24 8:15 ` Ingo Molnar
2017-11-06 2:10 Stephen Rothwell
2017-11-06 13:09 ` Rafael J. Wysocki
2017-08-11 4:06 Stephen Rothwell
2017-09-04 4:43 ` Stephen Rothwell
2016-11-22 5:48 Stephen Rothwell
2016-06-09 4:34 Stephen Rothwell
2016-04-19 2:59 Stephen Rothwell
2016-03-15 1:55 Stephen Rothwell
2016-03-11 1:57 Stephen Rothwell
2016-03-11 13:51 ` Rafael J. Wysocki
2016-02-29 4:42 Stephen Rothwell
2015-10-06 3:07 Stephen Rothwell
2015-03-31 7:58 Stephen Rothwell
2015-03-31 22:23 ` Rafael J. Wysocki
2015-03-31 7:10 Stephen Rothwell
2014-12-15 2:30 Stephen Rothwell
2014-11-25 5:46 Stephen Rothwell
2014-11-25 21:16 ` Rafael J. Wysocki
2014-08-04 6:55 Stephen Rothwell
2014-05-09 4:49 Stephen Rothwell
2014-01-13 3:29 Stephen Rothwell
2014-01-07 4:20 Stephen Rothwell
2014-01-06 7:18 Stephen Rothwell
2013-08-19 4:09 Stephen Rothwell
2013-04-11 4:08 Stephen Rothwell
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--in-reply-to=20240717114155.1a3d4c07@canb.auug.org.au \
--to=sfr@canb$(echo .)auug.org.au \
--cc=Xiaojian.Du@amd$(echo .)com \
--cc=bp@alien8$(echo .)de \
--cc=hpa@zytor$(echo .)com \
--cc=linux-kernel@vger$(echo .)kernel.org \
--cc=linux-next@vger$(echo .)kernel.org \
--cc=mario.limonciello@amd$(echo .)com \
--cc=mingo@redhat$(echo .)com \
--cc=perry.yuan@amd$(echo .)com \
--cc=peterz@infradead$(echo .)org \
--cc=rafael.j.wysocki@intel$(echo .)com \
--cc=rjw@rjwysocki$(echo .)net \
--cc=srinivas.pandruvada@linux$(echo .)intel.com \
--cc=tglx@linutronix$(echo .)de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
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