Subject: linux-next: manual merge of the scsi tree with the rockchip tree

From: Stephen Rothwell <[email-masked]>
Date: Tue, 11 Mar 2025 18:35:24 +1100

Hi all,

Today's linux-next merge of the scsi tree got a conflict in:

  arch/arm64/boot/dts/rockchip/rk3576.dtsi

between commit:

  36299757129c ("arm64: dts: rockchip: Add SFC nodes for rk3576")

from the rockchip tree and commit:

  c75e5e010fef ("scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC")

from the scsi tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/arm64/boot/dts/rockchip/rk3576.dtsi
index edfa0326f299,bd55bd8a67cb..000000000000
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@@ -1334,17 -1221,30 +1334,41 @@@
  			};
  		};
  
 +		sfc1: spi@2a300000 {
 +			compatible = "rockchip,sfc";
 +			reg = <0x0 0x2a300000 0x0 0x4000>;
 +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 +			clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
 +			clock-names = "clk_sfc", "hclk_sfc";
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			status = "disabled";
 +		};
 +
+ 		ufshc: ufshc@2a2d0000 {
+ 			compatible = "rockchip,rk3576-ufshc";
+ 			reg = <0x0 0x2a2d0000 0x0 0x10000>,
+ 			      <0x0 0x2b040000 0x0 0x10000>,
+ 			      <0x0 0x2601f000 0x0 0x1000>,
+ 			      <0x0 0x2603c000 0x0 0x1000>,
+ 			      <0x0 0x2a2e0000 0x0 0x10000>;
+ 			reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
+ 			clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
+ 				 <&cru CLK_REF_UFS_CLKOUT>;
+ 			clock-names = "core", "pclk", "pclk_mphy", "ref_out";
+ 			assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
+ 			assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
+ 			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ 			power-domains = <&power RK3576_PD_USB>;
+ 			pinctrl-0 = <&ufs_refclk>;
+ 			pinctrl-names = "default";
+ 			resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
+ 				 <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
+ 			reset-names = "biu", "sys", "ufs", "grf";
+ 			reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
+ 			status = "disabled";
+ 		};
+ 
  		sdmmc: mmc@2a310000 {
  			compatible = "rockchip,rk3576-dw-mshc";
  			reg = <0x0 0x2a310000 0x0 0x4000>;