Subject: linux-next: manual merge of the kvm-arm tree with the arm64 tree

From: Stephen Rothwell <[email-masked]>
Date: Mon, 17 Mar 2025 17:04:04 +1100

Hi all,

Today's linux-next merge of the kvm-arm tree got a conflict in:

  arch/arm64/kernel/cpufeature.c

between commits:

  f4fe70cd8522 ("arm64: cpufeature: factor out cpu_is_meltdown_safe()")
  837dfd070e94 ("arm64: cpufeature: mitigate CVE-2024-7881")

from the arm64 tree and commit:

  e3121298c7fc ("arm64: Modify _midr_range() functions to read MIDR/REVIDR internally")

from the kvm-arm tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/arm64/kernel/cpufeature.c
index f5ca9a535eba,9c4d6d552b25..000000000000
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -1787,63 -1791,15 +1789,63 @@@ static bool cpu_is_meltdown_safe(void
  		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
  		{ /* sentinel */ }
  	};
 +
- 	if (is_midr_in_range_list(read_cpuid_id(), meltdown_safe_list))
++	if (is_midr_in_range_list(meltdown_safe_list))
 +		return true;
 +
 +	/*
 +	 * ID_AA64PFR0_EL1.CSV3 > 0 indicates that this CPU is not vulnerable
 +	 * to meltdown.
 +	 */
 +	pfr0 = __read_sysreg_by_encoding(SYS_ID_AA64PFR0_EL1);
 +	if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_CSV3_SHIFT))
 +		return true;
 +
 +	return false;
 +}
 +
 +static bool cpu_has_leaky_prefetcher(void)
 +{
 +	struct arm_smccc_res res;
 +
 +	/* CPUs which are affected by CVE-2024-7881 */
 +	static const struct midr_range leaky_prefetcher_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
 +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
 +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
 +		{ /* sentinel */ }
 +	};
 +
- 	if (!is_midr_in_range_list(read_cpuid_id(), leaky_prefetcher_list))
++	if (!is_midr_in_range_list(leaky_prefetcher_list))
 +		return false;
 +
 +	/*
 +	 * If ARCH_WORKAROUND_4 is implemented, then the firmware mitigation is
 +	 * present. There is no need to call ARCH_WORKAROUND_4 itself.
 +	 */
 +	arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 +			     ARM_SMCCC_ARCH_WORKAROUND_4, &res);
 +	if (res.a0 == SMCCC_RET_SUCCESS)
 +		return false;
 +
 +	return true;
 +}
 +
 +static bool __meltdown_safe = true;
 +static bool __leaky_prefetch_safe = true;
 +static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 +
 +static bool needs_kpti(const struct arm64_cpu_capabilities *entry, int scope)
 +{
  	char const *str = "kpti command line option";
  	bool meltdown_safe;
 +	bool prefetcher_safe;
  
 -	meltdown_safe = is_midr_in_range_list(kpti_safe_list);
 -
 -	/* Defer to CPU feature registers */
 -	if (has_cpuid_feature(entry, scope))
 -		meltdown_safe = true;
 +	WARN_ON(scope != SCOPE_LOCAL_CPU);
  
 +	meltdown_safe = cpu_is_meltdown_safe();
  	if (!meltdown_safe)
  		__meltdown_safe = false;