Subject: linux-next: manual merge of the kvm-arm tree with the arm64 tree

From: Stephen Rothwell <[email-masked]>
Date: Mon, 17 Mar 2025 17:17:01 +1100

Hi all,

Today's linux-next merge of the kvm-arm tree got a conflict in:

  arch/arm64/kernel/proton-pack.c

between commits:

  e403e8538359 ("arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB")
  a5951389e58d ("arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists")

from the arm64 tree and commit:

  e3121298c7fc ("arm64: Modify _midr_range() functions to read MIDR/REVIDR internally")

from the kvm-arm tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/arm64/kernel/proton-pack.c
index 0f51fd10b4b0,a573fa40d4b6..000000000000
--- a/arch/arm64/kernel/proton-pack.c
+++ b/arch/arm64/kernel/proton-pack.c
@@@ -845,86 -845,52 +845,86 @@@ static unsigned long system_bhb_mitigat
   * This must be called with SCOPE_LOCAL_CPU for each type of CPU, before any
   * SCOPE_SYSTEM call will give the right answer.
   */
 -u8 spectre_bhb_loop_affected(int scope)
 +static bool is_spectre_bhb_safe(int scope)
 +{
 +	static const struct midr_range spectre_bhb_safe_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A510),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A520),
 +		MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
 +		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
 +		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
 +		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
 +		{},
 +	};
 +	static bool all_safe = true;
 +
 +	if (scope != SCOPE_LOCAL_CPU)
 +		return all_safe;
 +
- 	if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_safe_list))
++	if (is_midr_in_range_list(spectre_bhb_safe_list))
 +		return true;
 +
 +	all_safe = false;
 +
 +	return false;
 +}
 +
 +static u8 spectre_bhb_loop_affected(void)
  {
  	u8 k = 0;
 -	static u8 max_bhb_k;
  
 -	if (scope == SCOPE_LOCAL_CPU) {
 -		static const struct midr_range spectre_bhb_k32_list[] = {
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
 -			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 -			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
 -			{},
 -		};
 -		static const struct midr_range spectre_bhb_k24_list[] = {
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
 -			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
 -			{},
 -		};
 -		static const struct midr_range spectre_bhb_k11_list[] = {
 -			MIDR_ALL_VERSIONS(MIDR_AMPERE1),
 -			{},
 -		};
 -		static const struct midr_range spectre_bhb_k8_list[] = {
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 -			MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 -			{},
 -		};
 +	static const struct midr_range spectre_bhb_k132_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
 +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
 +	};
 +	static const struct midr_range spectre_bhb_k38_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
 +	};
 +	static const struct midr_range spectre_bhb_k32_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
 +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
 +		{},
 +	};
 +	static const struct midr_range spectre_bhb_k24_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
 +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
 +		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD),
 +		{},
 +	};
 +	static const struct midr_range spectre_bhb_k11_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
 +		{},
 +	};
 +	static const struct midr_range spectre_bhb_k8_list[] = {
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 +		{},
 +	};
  
- 	if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k132_list))
 -		if (is_midr_in_range_list(spectre_bhb_k32_list))
 -			k = 32;
 -		else if (is_midr_in_range_list(spectre_bhb_k24_list))
 -			k = 24;
 -		else if (is_midr_in_range_list(spectre_bhb_k11_list))
 -			k = 11;
 -		else if (is_midr_in_range_list(spectre_bhb_k8_list))
 -			k =  8;
 -
 -		max_bhb_k = max(max_bhb_k, k);
 -	} else {
 -		k = max_bhb_k;
 -	}
++	if (is_midr_in_range_list(spectre_bhb_k132_list))
 +		k = 132;
- 	else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k38_list))
++	else if (is_midr_in_range_list(spectre_bhb_k38_list))
 +		k = 38;
- 	else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list))
++	else if (is_midr_in_range_list(spectre_bhb_k32_list))
 +		k = 32;
- 	else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
++	else if (is_midr_in_range_list(spectre_bhb_k24_list))
 +		k = 24;
- 	else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list))
++	else if (is_midr_in_range_list(spectre_bhb_k11_list))
 +		k = 11;
- 	else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))
++	else if (is_midr_in_range_list(spectre_bhb_k8_list))
 +		k =  8;
  
  	return k;
  }