Subject: linux-next: manual merge of the risc-v tree with the mm-stable tree

From: Stephen Rothwell <[email-masked]>
Date: Wed, 26 Nov 2025 09:48:30 +1100

Hi all,

Today's linux-next merge of the risc-v tree got a conflict in:

  arch/riscv/include/asm/hwcap.h

between commit:

  59f6acb4be02 ("riscv: add RISC-V Svrsw60t59b extension support")

from the mm-stable tree and commits:

  c9651fbc6051 ("riscv: Add ISA extension parsing for Zalasr")
  ac3b03f8a4eb ("riscv: add ISA extension parsing for Zilsd and Zclsd")

from the risc-v tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/riscv/include/asm/hwcap.h
index f98fcb5c17d5,bfba183e6290..000000000000
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -106,7 -106,9 +106,10 @@@
  #define RISCV_ISA_EXT_ZAAMO		97
  #define RISCV_ISA_EXT_ZALRSC		98
  #define RISCV_ISA_EXT_ZICBOP		99
- #define RISCV_ISA_EXT_SVRSW60T59B	100
+ #define RISCV_ISA_EXT_ZALASR		100
+ #define RISCV_ISA_EXT_ZILSD		101
+ #define RISCV_ISA_EXT_ZCLSD		102
++#define RISCV_ISA_EXT_SVRSW60T59B	103
  
  #define RISCV_ISA_EXT_XLINUXENVCFG	127