Subject: linux-next: manual merge of the tip tree with the risc-v tree

From: Mark Brown <[email-masked]>
Date: Thu, 22 Jan 2026 15:32:25 +0000

Hi all,

Today's linux-next merge of the tip tree got conflicts in:

  include/uapi/linux/prctl.h
  kernel/sys.c

between commit:

  d3d1efd48b3b6 ("prctl: add arch-agnostic prctl()s for indirect branch tracking")

from the risc-v tree and commit:

  28621ec2d46c6 ("rseq: Add prctl() to enable time slice extensions")

from the tip tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc include/uapi/linux/prctl.h
index f57098fb0ba8b,79944b7ae50aa..0000000000000
--- a/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@@ -386,31 -386,14 +386,41 @@@ struct prctl_mm_map 
  # define PR_FUTEX_HASH_SET_SLOTS	1
  # define PR_FUTEX_HASH_GET_SLOTS	2
  
 +/*
 + * Get the current indirect branch tracking configuration for the current
 + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS.
 + */
 +#define PR_GET_INDIR_BR_LP_STATUS      79
 +
 +/*
 + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will
 + * enable cpu feature for user thread, to track all indirect branches and ensure
 + * they land on arch defined landing pad instruction.
 + * x86 - If enabled, an indirect branch must land on an ENDBRANCH instruction.
 + * arch64 - If enabled, an indirect branch must land on a BTI instruction.
 + * riscv - If enabled, an indirect branch must land on an lpad instruction.
 + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect
 + * branches will no more be tracked by cpu to land on arch defined landing pad
 + * instruction.
 + */
 +#define PR_SET_INDIR_BR_LP_STATUS      80
 +# define PR_INDIR_BR_LP_ENABLE		   (1UL << 0)
 +
 +/*
 + * Prevent further changes to the specified indirect branch tracking
 + * configuration.  All bits may be locked via this call, including
 + * undefined bits.
 + */
 +#define PR_LOCK_INDIR_BR_LP_STATUS      81
 +
+ /* RSEQ time slice extensions */
 -#define PR_RSEQ_SLICE_EXTENSION			79
++#define PR_RSEQ_SLICE_EXTENSION			82
+ # define PR_RSEQ_SLICE_EXTENSION_GET		1
+ # define PR_RSEQ_SLICE_EXTENSION_SET		2
+ /*
+  * Bits for RSEQ_SLICE_EXTENSION_GET/SET
+  * PR_RSEQ_SLICE_EXT_ENABLE:	Enable
+  */
+ # define PR_RSEQ_SLICE_EXT_ENABLE		0x01
+ 
  #endif /* _LINUX_PRCTL_H */
diff --cc kernel/sys.c
index 9071422c16096,35ea9d79a42e4..0000000000000
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@@ -2883,21 -2868,11 +2883,26 @@@ SYSCALL_DEFINE5(prctl, int, option, uns
  	case PR_FUTEX_HASH:
  		error = futex_hash_prctl(arg2, arg3, arg4);
  		break;
 +	case PR_GET_INDIR_BR_LP_STATUS:
 +		if (arg3 || arg4 || arg5)
 +			return -EINVAL;
 +		error = arch_get_indir_br_lp_status(me, (unsigned long __user *)arg2);
 +		break;
 +	case PR_SET_INDIR_BR_LP_STATUS:
 +		if (arg3 || arg4 || arg5)
 +			return -EINVAL;
 +		error = arch_set_indir_br_lp_status(me, arg2);
 +		break;
 +	case PR_LOCK_INDIR_BR_LP_STATUS:
 +		if (arg3 || arg4 || arg5)
 +			return -EINVAL;
 +		error = arch_lock_indir_br_lp_status(me, arg2);
 +		break;
+ 	case PR_RSEQ_SLICE_EXTENSION:
+ 		if (arg4 || arg5)
+ 			return -EINVAL;
+ 		error = rseq_slice_extension_prctl(arg2, arg3);
+ 		break;
  	default:
  		trace_task_prctl_unknown(option, arg2, arg3, arg4, arg5);
  		error = -EINVAL;