Subject: mpc5200 i2c bus problem

From: "Frederic Janot" <[email-masked]>
Date: Mon, 4 Jul 2005 11:45:23 +0200

Hi all,

I send a message here to indicate an hardware problem with mpc5200 i2c
module. This bug is not describe in the mpc5200 errata document.
I can reproduce it on revA and revB of the silicium. After contacting
Freescale, they recognize the problem.

The problem is that, sometime, the 9th pulse clock on SCL is missing !!!!
I can send a scope screen capture which shows that if someone wants.

When it happens, the slave does not release SDA bus because it waits to send
its acknowledge
=> the bus is locked (we cannot get slave status and we cannot generate stop
condition to release the bus)

The problem appears more frequently with IPB clock at 132MHz than with IPB
clock at 66MHz (looks like a timing problem into i2c module)
Freescale advice to set i2c clock at 86 kHz but the problem still appears
with my board !

I used a kernel based on Denk's one (2.4.25). The i2c driver call
wait_for_bb (bus busy) with a timeout. When the bus is locked, this function
always return with an error code => no more i2c transferts possible.

To workaround this problem, the solution is to "manually" generate the 9th
pulse clock.

The sequence is the following :
mcr = 0x00 (disable i2c module)
mcr = 0x80 (re-enable i2c module)
mcr = 0x30 (re-disabling i2c bus, it makes SCL goes high)          => not
really sure if we should send 0x30 or if 0x00 is enough, I will try
mcr = 0xb0 (generate a start condition, it makes SCL goes low)
mcr = 0x80 (generate a stop condition, it makes SCL goes high)

After that, the bus is available again.
We have to re-send last i2c transfert (the one which locked the bus) because
we can not be sure that slave well understand the i2c request.

Hope it can help,
Frederic