Subject: Re: dynamic modification exception handler

From: "kerler" <[email-masked]>
Date: Tue, 27 Feb 2001 10:08:52 +0800

Hi,

I add sync between icbi and isync. But the executed codes are still the
stale codes. Is cache coherence related with address translation of MMU?

-----------method 2----------
static inline void store_inst(void *p)
{
    asm volatile ("dcbst 0,%0; sync; icbi 0,%0; sync; isync" : : "r" (p));
}
void mdb_flush_cache (const unsigned int start, const unsigned int len)
{
    unsigned int i;
    for ( i = start ; i <= len + start ; i ++ )
    {
        store_inst((void*)start);
    }
}
------------end of method 2------

----- Original Message -----
From: David Edelsohn <[email-masked]>
To: kerler <[email-masked]>
Cc: <[email-masked]>
Sent: Tuesday, February 27, 2001 2:35 AM
Subject: Re: dynamic modification exception handler

>
> The suggested sequence for 604 and 604-derived processors is:
>
>      dcbst (or dcbf)          ;# flush data block to memory
>      sync                     ;# ensure flush made it to memory
>      icbi                     ;# invalidate block from icache
>      sync                     ;# wait for icbi to be globally performed
>      isync                    ;# refetch instructions
>
> The dcbst must be performed before the icbi, because otherwise the
> processor instruction prefetch mechanism could refetch the (stale) block
> from memory before the dcbst/dcbf has actually been written back to
> memory.  The sync between them is required for the same reason, because
> icbi could be performed locally before the dcbst has sent the block to
> memory.
>
> The dcbst/sync/icbi sequence can be batched up to amortize the
> cost of the sync operations, but it should be written so all the dcbst's
> are performed, then a sync, then all the icbi's:
>
>      mr        r5, r3
>      mtctr     blocks
> $1:
>      dcbst     r0, r5
>      addi      r5, r5, 32
>      bdnz      $1
>      sync
>      mr        r5, r3
>      mtctr     blocks
> $2:
>      icbi      r0, r5
>      addi      r5, r5, 32
>      bdnz      $2
>
>      sync
>      isync
>
>
> David
>
>

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