Subject: PowerPC + SMP

From: "Stuart Yoder" <[email-masked]>
Date: Mon, 25 Apr 2005 16:11:08 -0500

Hi.
 
I am trying to figure out where in the PowerPC kernel the HID1 register
is updated to enable bits dealing with cache coherency in an SMP system.
Grepping through the arch/ppc source does not reveal much.
 
I have two 7447A processors and somewhere the ABE and SYNCBE bits need
to be turned on to enable cache coherency.   Is supposed to happen in
the bootloader prior to the kernel running??
 
Thanks,
Stuart Yoder