Subject: RE: PowerPC + SMP

From: "Stuart Yoder" <[email-masked]>
Date: Tue, 26 Apr 2005 14:16:14 -0500

Thanks Kumar.

How can I know what assumptions the kernel makes about the state of the
CPU/system when it begins execution? Is this clearly documented
anywhere?

Do you know of open source bootloaders for Linux that would demonstrate
how to set up the CPUs as the Linux kernel expects.

Thanks,
Stuart

> -----Original Message-----
> From: Kumar Gala [mailto:[email-masked]]=20
> Sent: Monday, April 25, 2005 4:40 PM
> To: Stuart Yoder
> Cc: [email-masked]
> Subject: Re: PowerPC + SMP
>=20
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> On Apr 25, 2005, at 4:10 PM, Stuart Yoder wrote:
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> > Hi.
> > =A0
> > I am trying to figure out where in the PowerPC kernel the HID1
> > register is updated to enable bits dealing with cache=20
> coherency in an=20
> > SMP system.=A0=A0 Grepping through the arch/ppc source does not =
reveal=20
> > much.
> > =A0
> > I have=A0two 7447A processors and somewhere the ABE and SYNCBE bits =
in
> > HID1=A0need to be turned on to enable cache coherency.=A0=A0 Is=20
> supposed to=20
> > happen in the bootloader prior to the kernel running??
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> The expectation is that the bootloader normally handles such things.
>=20
> - kumar
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