From: Yuri Tikhonov <yur@emcraft•com>
To: Benjamin Herrenschmidt <benh@kernel•crashing.org>
Cc: linuxppc-dev@ozlabs•org
Subject: Re[2]: [PATCH] [PPC 44x] L2-cache synchronization for ppc44x
Date: Thu, 8 Nov 2007 02:39:05 +0300 [thread overview]
Message-ID: <1021205055.20071108023905@emcraft.com> (raw)
In-Reply-To: <1194477573.6523.58.camel@pasglop>
Hi Ben,
On 08.11.2007, 2:19:33 you wrote:
> On Thu, 2007-11-08 at 02:12 +0300, Yuri Tikhonov wrote:
>> This is the updated patch for support synchronization of L2-Cache with
>> the external memory on the ppc44x-based platforms.
>>
>> Differencies against the previous patch-set:
>> - remove L2_CACHE config option;
>> - introduce the ppc machdep to invalidate L2 cache lines;
>> - some code clean-up.
> Can you tell me more about how this cache operates ? I don't quite
> understand why you would invalidate it on bidirectional DMAs rather than
> flush it to memory (unless you get your terminology wrong) and why you
> wouldn't flush it on transfers to the device.. Unless it is a
> write-through cache ?
Yes, the ppc44x Level2 cache has the write-through design, so no need to do any kind of l2_flush.
As far as the DMA_BIDIRECTIONAL case is concerned flush_dcache_range() flushes the data over the following path: L1->L2->RAM, but invalidates L1 only, and L2 remains invalid. Since in the BIDIRECTIONAL case DMA may update the data in RAM - we have to invalidate L2-cache manually, so that CPU may read new data transmitted by DMA right from RAM rather than old ones stuck in L2 due to flush_dcache().
Regards,
Yuri
--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com
next prev parent reply other threads:[~2007-11-07 23:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-11-07 23:12 [PATCH] [PPC 44x] L2-cache synchronization for ppc44x Yuri Tikhonov
2007-11-07 23:19 ` Benjamin Herrenschmidt
2007-11-07 23:39 ` Yuri Tikhonov [this message]
2007-11-26 6:47 ` Benjamin Herrenschmidt
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