From: Jim Rowe <rowejames@acmsystems•com>
To: linuxppc-embedded@lists•linuxppc.org
Subject: PCI interrupt masking, CSR on the MPC8250
Date: 26 May 2003 05:37:18 -0700 [thread overview]
Message-ID: <1053952637.3773.26.camel@kneedragger> (raw)
Hello,
I have a question on some of Dan's code for the PCI support of the
MPC8266.
The kernel is crashing at boot on my MPC8250 when the PCI interrupts are
being masked during boot in mpc8266ads_pci.c::mpc8266ads_init_irq(). The
line of code is
*(volatile) unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
PCI_INT_MASK_REG is defined in ads8260.h to be 0xf8200004. I've looked
through the MPC8260 User's Manual as well as the PCI Bridge addendum and
cannot find the register at this location. Where did this address come
from? Is this board specific? The only PCI Mask register that I found in
the documentation is named SIPNR_H located at IMAP_ADDR+0x10C08 (from
the PCI Bridge addendum section 1.7), and PCI has only one bit in here.
In the same header I also see that BCSR_ADDR is set to 0xf8000000. I
cannot find this area of memory or a description of the CSR in the
documentation. Judging by its address, I think I will get a Machine
Check here as well once the kernel gets that far. What exactly is a CSR?
Thanks for any help!
-- James
--
Jim Rowe
Advanced CounterMeasure Systems
Phone: (916)669-4304
Email: jrowe@acmsystems•com
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next reply other threads:[~2003-05-26 12:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-05-26 12:37 Jim Rowe [this message]
-- strict thread matches above, loose matches on Subject: below --
2003-05-26 18:13 PCI interrupt masking, CSR on the MPC8250 Andy Lowe
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