Subject: Re: PowerPC + SMP

From: Benjamin Herrenschmidt <[email-masked]>
Date: Tue, 26 Apr 2005 13:36:34 +1000

On Mon, 2005-04-25 at 16:11 -0500, Stuart Yoder wrote:
> Hi.
>  
> I am trying to figure out where in the PowerPC kernel the HID1
> register is updated to enable bits dealing with cache coherency in an
> SMP system.   Grepping through the arch/ppc source does not reveal
> much.
>  
> I have two 7447A processors and somewhere the ABE and SYNCBE bits need
> to be turned on to enable cache coherency.   Is supposed to happen in
> the bootloader prior to the kernel running??

It's usually expected to happen in the firmware yes, though the kernel
does some of it's own 'fixups' (look at setup_cpu_6xx.S)

Ben.