Subject: Re: [PATCH] [2/2] POWERPC: Lower threshold for DART enablement to 1GB, V2

From: Benjamin Herrenschmidt <[email-masked]>
Date: Sun, 16 Apr 2006 06:28:55 +1000

On Sat, 2006-04-15 at 08:37 -0500, Jon Mason wrote:
> On Sat, Apr 15, 2006 at 06:57:55AM +1000, Benjamin Herrenschmidt wrote:
> > 
> > > What I had in mind is an interface that given a PCI bridge will tell
> > > you what's the most restrictive DMA mask for a device on that bridge,
> > > so that you'll know whether you need to enable the IOMMU for that
> > > bridge. I'll even settle for a function that tells you what's the most
> > > restrictive DMA mask in the system, period. There's nothing inherently
> > > arch specific about this.
> > >
> > > (and as a side note, the IOMMU we are working on on x86-64 is Calgary,
> > > which is actually roughly the same chipset used in some PPC
> > > machines...)
> > 
> > Not sure I ever heard about that... What chipsets ?
> 
> The pSeries POWER4 based systems (Regatta) had Calgary, and the 
> RS/6000 POWER3 based systems (Condor) had Winnipeg (a precursor to
> Calgary, with many of the same features).

Ah ok, I'm not familiar with the IBM chipset names

Ben.