Subject: Re: [RFC/PATCH 14/16] MPIC MSI backend

From: Benjamin Herrenschmidt <[email-masked]>
Date: Sun, 28 Jan 2007 07:02:55 +1100

> My impression was any CPU that uses an IO-SAPIC (or -xAPIC) is
> using bus transactions to communicate interrupts even if they
> aren't using MSI. BIOS typically hides all the setup.
> 
> Alpha also uses bus transactions for IO interrupts. But I've read
> through my ancient alpha reference manual and don't understand
> exactly if the vector is part of the "DMA" transaction or is read
> by the CPU off the I/O Bridge ("hose").
> 
> > Or do you mean there is some piece of hardware in the northbridge (or
> > elsewhere) that accepts the MSI message writes and asserts an
> > interrupt line to the CPU?  That is basically what we have on PPC.
> 
> *grin* PPC in this case looks more like "legacy x86" than x86 does today.
> /me hides

Well, actually, Cell also has interrupts as packets on the bus :-)

(Though the way it's done on cell, you typically still need an external
interrupt controller for anything that's not on-chip unfortunately).

Ben.