Subject: Re: [patch 3/3] cell: prevent alignment interrupt on local store

From: Benjamin Herrenschmidt <[email-masked]>
Date: Thu, 12 Apr 2007 18:48:11 +1000

On Thu, 2007-04-12 at 10:31 +0200, Gabriel Paubert wrote:
> On Thu, Apr 12, 2007 at 04:38:10PM +1000, Benjamin Herrenschmidt wrote:
> > On Thu, 2007-04-12 at 08:33 +0200, Olaf Hering wrote:
> > > On Thu, Apr 12, Benjamin Herrenschmidt wrote:
> > > 
> > > > Gets altivec and stops working on POWER5 ? no deal :-)
> > > 
> > > If there is a significant performance gain (not only 9%) and if
> > > -mcpu=$cell does not generate instructions that wont work on other
> > > altivec capable cpus and if rpm gets a target ppcaltivec.rpm (or
> > > similar), as separate binary tree can be done.
> > 
> > -mcpu=cell can possibly generate things that won't run on 970 and 74xx.
> > There are some new altivec instructions among others...
> 
> Any pointer to a document describing the differences?

I'm not sure where this is documented. There are a few new ops for
doing load/save of partial vectors (to help handle edge cases),
there are some more precise implementation of some fp osp (though
that should be backward compatible), and maybe a few other things.

I think most public cell docs can be found at

http://www-306.ibm.com/chips/techlib/techlib.nsf/products/Cell_Broadband_Engine

Though I have no idea where those specifics are described.

Cheers,
Ben.