Subject: Re: [RFC/PATCH] powerpc: MPC7450 L2 HW cache flush feature utilization

From: Benjamin Herrenschmidt <[email-masked]>
Date: Thu, 28 Jun 2007 21:09:04 +1000

On Thu, 2007-06-28 at 14:47 +0400, Vladislav Buzov wrote:
> 
> I've looked through cache.S and see it contains a dcbf loop over 4Mb 
> along with L2, L3 HW cache flushing. The comments says 'Due to a bug 
> with the HW flush on some CPU revs, we occasionally experience data 
> corruption...'. Could you please clarify which CPU revisions have this 
> bug and whether it is the same bug described in errata and requiring a 
> complete cache locking before flushing? Do we still need to use the dcbf 
> loop in _set_L2CR() for MPC7450 processors?

Can't remember ... that code is pretty old now.

Cheers,
Ben.