Subject: Re: [PATCH 0/2] [PPC 4xx] L2-cache synchronization for ppc44x

From: Benjamin Herrenschmidt <[email-masked]>
Date: Sat, 12 Jan 2008 09:05:35 +1100

> >  The s/w synchronization algorithms proposed in my patches has no LL PLB 
> > limitations as opposed to h/w snooping, but, probably, this is not the best 
> > way of how it might be implemented. Even though with these patches the h/w 
> > accelerated RAID starts to operate correctly (with L2-cache enabled) there is 
> > a performance degradation (induced by loops in the L2-cache synchronization 
> > routines) observed in the most cases. So, as a result, there is no benefit 
> > from using L2-cache for these, RAID, cases at all.
> 
> Thanks a lot for explanation, Yuri. I'd never imagine they were so 
> stupid to make new chips with such behaviour.

Indeed. Now the question is do we want to make that configurable by the
platform so it can select whether to enable snooping, or use this
mechanism (in which case we can disable snooping on the L2) ?

Another option would be to make the dma_ops smart enough to know whether
a given device is on the snooped portion of the bus, which would be
easier to do after I merge 32 and 64 bits DMA ops, so we get the ability
to change the dma-ops per bus or per device even.

What do you guys think ?

Cheers,
Ben.