Subject: Re: [PATCH 1/2] [POWERPC] Add PPC4xx L2-cache support (440GX & 460EX/GT)

From: Benjamin Herrenschmidt <[email-masked]>
Date: Thu, 20 Mar 2008 17:54:52 +1100

On Tue, 2008-03-18 at 14:36 +0100, Stefan Roese wrote:
> This patch adds support for the 256k L2 cache found on some IBM/AMCC
> 4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
> which currently "only" adds the L2 cache init code. Other common 4xx
> stuff can be added later here.
> 
> The L2 cache handling code is just a copy of Eugene's code in arch/ppc
> with small modifications.
> 
> Tested on AMCC Taishan 440GX and Canyonlands 460EX.
> 
> Signed-off-by: Stefan Roese <[email-masked]>

It's my understanding that on some 44x platforms, the l2 needs to be
explicitely invalidated on DMAs. Do we know more about that ? I think it
depends on something like the number of masters on the PLB4 or so. I
don't remember the details.

Ben.