Subject: Re: [Cbe-oss-dev] [patch 11/11] powerpc/cell: Add DMA_ATTR_STRONG_ORDERING dma attribute and use in IOMMU code

From: Michael Ellerman <[email-masked]>
Date: Mon, 07 Jul 2008 10:00:51 +1000

On Sat, 2008-07-05 at 23:51 +0200, Arnd Bergmann wrote:
> On Saturday 05 July 2008, Benjamin Herrenschmidt wrote:
> > On Sat, 2008-07-05 at 15:43 +1000, Michael Ellerman wrote:
> > > > The current Cell IOMMU implementation sets the IOPTE_SO_RW bits in all IOTPEs
> > > > (for both the dynamic and fixed mappings) which enforces strong ordering of
> > > > both reads and writes. This patch makes the default behaviour weak ordering
> > > > (the IOPTE_SO_RW bits not set) and to request a strongly ordered mapping the
> > > > new DMA_ATTR_STRONG_ORDERING needs to be used.
> > > 
> > > We're sure that's safe?
> > 
> > I'd say it's not...
> 
> It turned out that the firmware sets up the south bridge to never set the 'S'
> bit on incoming transactions, which overrides the IOPTE_SO_RW bits, on all
> existing cell hardware.

It seems strange to me that the southbridge is allowed to override the
setting in the IOMMU page table, but if that's what the doc says ..

cheers

-- 
Michael Ellerman
OzLabs, IBM Australia Development Lab

wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)

We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person