Subject: Re: [PATCH v2] POWERPC: Allow 32-bit pgtable code to support 36-bit physical

From: Benjamin Herrenschmidt <[email-masked]>
Date: Mon, 01 Sep 2008 15:28:22 +1000

> Could the stw to the same reservation granule as the stwcx cancel the 
> reservation on some implementations?

It might I suppose ... In any case, see my replies to Becky.

>   Plus, if you're assuming that the 
> entry is currently invalid and all callers have the page table lock, do 
> we need the lwarx/stwcx at all?  At the least, it should check 
> PTE_ATOMIC_UPDATES.

It shouldn't need atomic operations -if- the current entry is invalid
-and- _PAGE_HASHPTE is clear. (Ie, the current entry is invalid -and- 
the hash table has been updated).

In any case, the stw can just move out of the loop.

It might be worth just doing something along the lines of

	if (pte_val(*ptep) & _PAGE_PRESENT)
		pte_clear(pte);
	if (pte_val(*ptep) & _PAGE_HASHPTE)
		flush_hash_entry(mm, ptep, addr);
	asm v. { "stw ; eieio; stw" };

Cheers,
Ben.