From: Aaron Sierra <asierra@xes-inc•com>
To: linuxppc-dev@lists•ozlabs.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation•org>,
Arnd Bergmann <arnd@arndb•de>,
Prabhakar Kushwaha <prabhakar@freescale•com>
Subject: [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects
Date: Fri, 15 Aug 2014 16:07:56 -0500 (CDT) [thread overview]
Message-ID: <1234993482.57039.1408136876321.JavaMail.zimbra@xes-inc.com> (raw)
Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.
Signed-off-by: Aaron Sierra <asierra@xes-inc•com>
---
include/linux/fsl_ifc.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index 84d60cb..62762ff 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -29,7 +29,7 @@
#include <linux/of_platform.h>
#include <linux/interrupt.h>
-#define FSL_IFC_BANK_COUNT 4
+#define FSL_IFC_BANK_COUNT 8
/*
* CSPR - Chip Select Property Register
@@ -776,23 +776,23 @@ struct fsl_ifc_regs {
__be32 cspr;
u32 res2;
} cspr_cs[FSL_IFC_BANK_COUNT];
- u32 res3[0x19];
+ u32 res3[0xd];
struct {
__be32 amask;
u32 res4[0x2];
} amask_cs[FSL_IFC_BANK_COUNT];
- u32 res5[0x18];
+ u32 res5[0xc];
struct {
__be32 csor;
__be32 csor_ext;
u32 res6;
} csor_cs[FSL_IFC_BANK_COUNT];
- u32 res7[0x18];
+ u32 res7[0xc];
struct {
__be32 ftim[4];
u32 res8[0x8];
} ftim_cs[FSL_IFC_BANK_COUNT];
- u32 res9[0x60];
+ u32 res9[0x30];
__be32 rb_stat;
u32 res10[0x2];
__be32 ifc_gcr;
--
1.9.1
next reply other threads:[~2014-08-15 21:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-15 21:07 Aaron Sierra [this message]
2014-08-20 0:08 ` [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects Scott Wood
2014-08-20 3:35 ` Prabhakar Kushwaha
2014-08-20 15:54 ` Aaron Sierra
2014-08-20 23:21 ` Scott Wood
2014-08-22 14:37 ` Prabhakar Kushwaha
2014-08-22 17:51 ` Scott Wood
2014-08-25 6:28 ` Prabhakar Kushwaha
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