Subject: Re: PPC PCI bus registers

From: Benjamin Herrenschmidt <[email-masked]>
Date: Thu, 17 Sep 2009 07:54:46 +1000

On Wed, 2009-09-16 at 11:58 -0700, Eddie Dawydiuk wrote:
> I'm not sure I understand. To clarify I have an FPGA connected via the
> PCI bus 
> which implements several peripherals, I've implemented device drivers
> for. 
> Currently I am calling ioremap() to get a virtual address
> corresponding to the 
> PCI devices. Then I use ___raw_writeN / ___raw_readN for
> reading/writing data 
> via the PCI bus to the FPGA registers. From looking at io.h I believe
> this 
> method is safe with regard to out of order execution.
> 
> "* ioremap is the standard one and provides non-cacheable guarded
> mappings
> *   and can be hooked by the platform via ppc_md "
> 
> Can you verify if my understanding is correct, or let me know if I
> need to add 
> memory barriers?
> 

Out of order execution != out of order storage. ioremap() will give you
guarded space which means it cannot be speculatively accessed for
example, and you do get -some- guarantees but not that your stores are
going to hit the device in order, nor that your loads are going to be
performed until the CPU actually use the result of the load, which can
be delayed beyond a store.

Cheers,
Ben.