Subject: Re: [PATCH 2/7] powerpc/mm: 64-bit 4k: use a PMD-based virtual page table

From: Benjamin Herrenschmidt <[email-masked]>
Date: Sat, 21 May 2011 08:15:36 +1000

On Fri, 2011-05-20 at 15:57 -0500, Scott Wood wrote:

> I see a 2% cost going from virtual pmd to full 4-level walk in the
> benchmark mentioned above (some type of sort), and just under 3% in
> page-stride lat_mem_rd from lmbench.
> 
> OTOH, the virtual pmd approach still leaves the possibility of taking a
> bunch of virtual page table misses if non-localized accesses happen over a
> very large chunk of address space (tens of GiB), and we'd have one fewer
> type of TLB miss to worry about complexity-wise with a straight table walk.
> 
> Let me know what you'd prefer.

I'm tempted to kill the virtual linear feature alltogether.. it didn't
buy us that much. Have you looked if you can snatch back some of those
cycles with hand tuning of the level walker ?

Would it work/help to have a simple cache of the last pmd & address and
compare just that ? Maybe in a SPRG or a known cache hot location like
the PACA in a line that we already load anyways ?

Cheers,
Ben.