Subject: Re: Semantics of lv1_pause()

From: Geoff Levand <[email-masked]>
Date: Tue, 10 Jul 2012 12:36:06 -0700

Hi Ben,

On Tue, 2012-07-10 at 13:20 +1000, Benjamin Herrenschmidt wrote:
> regarding the precise semantics of lv1_pause() ?

Here's what's in PS3's setup.c:

static void ps3_power_save(void)
{
	/*
	 * lv1_pause() puts the PPE thread into inactive state until an
	 * irq on an unmasked plug exists. MSR[EE] has no effect.
	 * flags: 0 = wake on DEC interrupt, 1 = ignore DEC interrupt.
	 */

	lv1_pause(0);
}

Just FYI, setup.c is here:

  http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/powerpc/platforms/ps3/setup.c;hb=HEAD#l72

> I'm fixing various issues with our idle loops, among other things,
> because we are soft-disabled when we hit ppc_md.powersave() but not
> hard-disabled, there could be an interrupt marked as pending and not
> taken yet.
> 
> Will that work properly ? I have this understanding that it might
> not ... but heh.

The (virtual) HW thread that called lv1_pause() should become active
when any virq that had irq_chip.irq_unmask() called for it occurs.

I'm not sure what 'become active' means if that virq is setup to be
handled by the 'paused' HW thread.  I guess the behavior depends on
if MSR_EE was set?
 
> Also if I call lv1_pause() with MSR_EE off, will it work ? Will it
> return with MSR_EE on like H_CEDE does on pseries ?

As above, the value of MSR_EE has no effect on activating the HW
thread, and I assume MSR_EE will still be off when lv1_pause() returns.
We can try some experiments if needed.

-Geoff