Subject: Re: [PATCH 1/4] powerpc/book3e: introduce external_input_edge exception handler for 64bit kernel

From: Scott Wood <[email-masked]>
Date: Wed, 15 May 2013 16:30:26 -0500

On 05/13/2013 09:03:17 PM, Kevin Hao wrote:
> On Mon, May 13, 2013 at 10:47:17AM -0500, Scott Wood wrote:
> > On 05/11/2013 06:26:21 PM, Kevin Hao wrote:
> > >In the external proxy facility mode, the interrupt is automatically
> > >acknowledged with the same effect as reading the IACK register. So
> > >this makes external input interrupt more like edge sensitive. That
> > >means we can leave the irq hard enabled when it occurs with irq =20
> soft
> > >disabled just like the dec and doorbell interrupt. But the External
> > >Proxy Register(EPR) is only considered valid from the time that the
> > >external interrupt occurs until MSR[EE] is set to 1. So we have to
> > >save the EPR before irq hard enabled.
> >
> > Is it really worth it?
>=20
> Maybe. :-)
> Compare with the current kernel:
>   * The overhead is that we need additional load & store the contents =20
> of
>     the EPR from/to PACA.

There's also mental overhead of the extra complexity.  The lazy EE =20
stuff is already fiddly enough (e.g. the recent KVM patches).

>   * The bonus is we keep the irq hard enabled when a external =20
> interrupt occurs
>     with irq soft-disabled. As I know we should leave the irq hard =20
> enabled as
>     much as possible. This is also the primary reason that we =20
> introduce the
>     Lazy EE.

I don't think "as much as possible" is a good way to look at it, so =20
much as "as much as is practical", balanced by also wanting to keep the =20
code as simple as is practical.

-Scott=