Subject: Re: Inbound PCI and Memory Corruption

From: Benjamin Herrenschmidt <[email-masked]>
Date: Mon, 24 Jun 2013 11:16:13 +1000

On Sun, 2013-06-23 at 17:56 -0700, Peter LaDow wrote:
> 
> On Jun 22, 2013, at 5:00 PM, Benjamin Herrenschmidt
> <[email-masked]> wrote:
> 
> > On Fri, 2013-06-21 at 10:14 -0700, Peter LaDow wrote:
> >> 
> > Afaik e300 is slightly out of order, maybe it's missing a memory
> barrier
> > somewhere.... One thing to try is to add some to the dma_map/unmap
> ops.
> > 
> > Also audit the driver to ensure that it properly uses barriers when
> > populating descriptors (and maybe compare to a more recent version
> of
> > the driver upstream).
> Thanks for the tips.
> 
> I've been working with the folk at Intel on the e1000-dev list, and
> they did add memory barriers. And I've tried the latest e1000 drivers
> (direct from the e1000 tree) with no luck.
> 
> I've done PCI traces, and there is no DMA after the disable is written
> to the e1000 part. All I can think is that there may be posted writes,
> the kernel goes on to cleanup the DMA buffers. But there are write
> memory barriers, so I don't see how this is possible.
> 
> Are the memory barriers meaningful in single processor builds?

Yes. However they have no effect on posted writes by the chip. You
need to do an MMIO read for these to take effect.

Also dbl check that the MMU is indeed mapping all these pages with the
"M" bit.

Cheers,
Ben.