From: Scott Wood <scottwood@freescale•com>
To: Tiejun Chen <tiejun.chen@windriver•com>
Cc: linuxppc-dev@lists•ozlabs.org, linux-kernel@vger•kernel.org
Subject: Re: [v3][PATCH 4/8] book3e/kexec/kdump: create a 1:1 TLB mapping
Date: Tue, 17 Dec 2013 21:39:45 -0600 [thread overview]
Message-ID: <1387337985.3140.35.camel@snotra.buserror.net> (raw)
In-Reply-To: <1373357007-30785-5-git-send-email-tiejun.chen@windriver.com>
On Tue, 2013-07-09 at 16:03 +0800, Tiejun Chen wrote:
> book3e have no real MMU mode so we have to create a 1:1 TLB
> mapping to make sure we can access the real physical address.
> And correct something to support this pseudo real mode on book3e.
>
> Signed-off-by: Tiejun Chen <tiejun.chen@windriver•com>
Why do we need to be able to directly access physical addresses?
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index f1a7ce7..20cbb98 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -460,6 +460,49 @@ kexec_flag:
>
>
> #ifdef CONFIG_KEXEC
> +#ifdef CONFIG_PPC_BOOK3E
> +/* BOOK3E have no a real MMU mode so we have to setup the initial TLB
> + * for a core to map v:0 to p:0 as 1:1. This current implementation
> + * assume that 1G is enough for kexec.
> + */
> +#include <asm/mmu.h>
#includes go at the top of the file.
> +kexec_create_tlb:
> + /* Invalidate all TLBs to avoid any TLB conflict. */
> + PPC_TLBILX_ALL(0,R0)
> + sync
> + isync
> +
> + mfspr r10,SPRN_TLB1CFG
> + andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */
> + subi r10,r10,1 /* Often its always safe to use last */
> + lis r9,MAS0_TLBSEL(1)@h
> + rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */
Hardcoding TLB1 makes this FSL-specific code, but you've put it in a
non-FSL-specific place.
> +/* Setup a temp mapping v:0 to p:0 as 1:1 and return to it.
> + */
> +#ifdef CONFIG_SMP
> +#define M_IF_SMP MAS2_M
> +#else
> +#define M_IF_SMP 0
> +#endif
> + mtspr SPRN_MAS0,r9
> +
> + lis r9,(MAS1_VALID|MAS1_IPROT)@h
> + ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
> + mtspr SPRN_MAS1,r9
What if the machine has less than 1 GiB of RAM? We could get
speculative accesses to non-present addresses.
Though it looks like the normal 64-bit init sequence has the same
problem...
-Scott
next prev parent reply other threads:[~2013-12-18 3:40 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-09 8:03 [v3][PATCH 0/8] powerpc/book3e: support kexec and kdump Tiejun Chen
2013-07-09 8:03 ` [v3][PATCH 1/8] powerpc/book3e: rename interrupt_end_book3e with __end_interrupts Tiejun Chen
2013-07-10 5:17 ` Bhushan Bharat-R65777
2013-07-10 5:39 ` tiejun.chen
2013-12-18 3:03 ` Scott Wood
2013-07-09 8:03 ` [v3][PATCH 2/8] powerpc/book3e: support CONFIG_RELOCATABLE Tiejun Chen
2013-12-18 3:29 ` Scott Wood
2013-07-09 8:03 ` [v3][PATCH 3/8] book3e/kexec/kdump: enable kexec for kernel Tiejun Chen
2013-12-18 3:35 ` Scott Wood
2013-07-09 8:03 ` [v3][PATCH 4/8] book3e/kexec/kdump: create a 1:1 TLB mapping Tiejun Chen
2013-12-18 3:39 ` Scott Wood [this message]
2013-07-09 8:03 ` [v3][PATCH 5/8] book3e/kexec/kdump: introduce a kexec kernel flag Tiejun Chen
2013-12-18 3:42 ` Scott Wood
2013-07-09 8:03 ` [v3][PATCH 6/8] book3e/kexec/kdump: implement ppc64 kexec specfic Tiejun Chen
2013-12-18 3:45 ` Scott Wood
2013-07-09 8:03 ` [v3][PATCH 7/8] book3e/kexec/kdump: redefine VIRT_PHYS_OFFSET Tiejun Chen
2013-07-10 5:20 ` Bhushan Bharat-R65777
2013-07-10 5:46 ` tiejun.chen
2013-12-18 3:48 ` Scott Wood
2013-07-09 8:03 ` [v3][PATCH 8/8] book3e/kexec/kdump: recover "r4 = 0" to create the initial TLB Tiejun Chen
2013-12-18 3:50 ` Scott Wood
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