Subject: Re: [PATCH V11 06/17] powerpc/pci: Add PCI resource alignment documentation

From: Benjamin Herrenschmidt <[email-masked]>
Date: Fri, 20 Feb 2015 13:41:35 +1100

On Thu, 2015-02-19 at 18:56 -0600, Bjorn Helgaas wrote:

> So there are the two windows of CPU address space that are routed to the
> PHB.  And the PHB contains one M32 window and sixteen M64 windows.  What
> happens if the PHB receives an access to something that was in one of the
> two CPU address space windows, but is not contained in M32 or one of the
> M64 windows?

Some kind of error, I don't know which one at this point, possibly fatal
(checkstop or similar) or maybe a fence of the PHB. Don't do it :-)

> If that is an error or is non-sensical, then the only windows relevant to
> PCI would be the M32 and M64 windows, and we could just ignore the
> top-level two windows.

Right. In fact we pretty much hard wire that one of the top level is
small and used for M32 with a fixed layout and the other is big and used
for all M64's. We use one of the M64 to cover it entirely, which is our
"base" set of segments for allocating busses/BARs, and then we use the
remaining M64's overlaid on top of that first one for things like
SR-IOV.

> I squashed all my doc updates into the original and pushed it here:
> 
> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/virtualization&id=5449d1a812d561bafe0d458132ef356765505507
> 
> If I made it say something wrong, a patch would be the best way to fix it.

Thanks, I'll have a look

Cheers,
Ben.