Subject: Re: question on FSL_EMB perf

From: Scott Wood <[email-masked]>
Date: Wed, 10 Jun 2015 15:13:56 -0500

On Wed, 2015-06-10 at 21:27 +0200, Peter Zijlstra wrote:
> On Wed, 2015-06-10 at 14:17 -0500, Scott Wood wrote:
> > On Wed, 2015-06-10 at 13:41 +0200, Peter Zijlstra wrote:
> > > Hi Mike, Ben,
> > > 
> > > I just noticed:
> > > 
> > > arch/powerpc/Kconfig:   select HAVE_PERF_EVENTS_NMI if PPC64
> > > 
> > > But can't ppc32 have FSL_EMB perf?
> > 
> > Yes, but it doesn't use NMIs.  ppc64 has lazy interrupt disabling 
> > which functions as a pseudo-NMI.
> 
> I know. But you can get the same nesting nonsense as with actual real
> NMIs.

What sort of "nesting nonsense" would we get on ppc32?  I wasn't 
trying to say that the pseudo-NMIs didn't count -- I was pointing out 
that we don't even have that on ppc32.

> And seeing how you select HAVE_PERF_EVENT_NMI for PPC64, I figure you
> ought to select it too for whatever fsl-emb is.

Why?

> # git grep nmi_enter arch/powerpc/
> arch/powerpc/perf/core-book3s.c:                nmi_enter();
> arch/powerpc/perf/core-fsl-emb.c:               nmi_enter();

nmi_enter() only gets called when perf_intr_is_nmi() returns non-zero, 
which only happens on ppc64.

-Scott