Subject: Re: [PATCH] cxl: Set endianess of kernel contexts

From: Michael Neuling <[email-masked]>
Date: Tue, 08 Dec 2015 14:11:41 +1100

On Mon, 2015-12-07 at 14:34 +0100, Frederic Barrat wrote:
> A process element (defined in CAIA) keeps track of the endianess of
> contexts through the Little Endian (LE) bit of the State Register. It
> is currently set for user contexts, but was somehow forgotten for
> kernel contexts, so this patch fixes it.
> It could lead to erratic behavior from an AFU when the context is
> attached through the kernel API.
>=20
> Signed-off-by: Frederic Barrat <[email-masked]>
> Suggested-by: Michael Neuling <[email-masked]>
> Cc: <[email-masked]> # 4.3+
> ---
> cxl kernel API is supported starting with 4.3 (for cxlflash)

The cxlflash's AFU doesn't use this bit, so the stable@ marker here is
probably not strictly needed.

Mikey

>  drivers/misc/cxl/native.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
> index d2e75c8..f409097 100644
> --- a/drivers/misc/cxl/native.c
> +++ b/drivers/misc/cxl/native.c
> @@ -497,6 +497,7 @@ static u64 calculate_sr(struct cxl_context *ctx)
>  {
>  	u64 sr =3D 0;
> =20
> +	set_endian(sr);
>  	if (ctx->master)
>  		sr |=3D CXL_PSL_SR_An_MP;
>  	if (mfspr(SPRN_LPCR) & LPCR_TC)
> @@ -506,7 +507,6 @@ static u64 calculate_sr(struct cxl_context *ctx)
>  		sr |=3D CXL_PSL_SR_An_HV;
>  	} else {
>  		sr |=3D CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
> -		set_endian(sr);
>  		sr &=3D ~(CXL_PSL_SR_An_HV);
>  		if (!test_tsk_thread_flag(current, TIF_32BIT))
>  			sr |=3D CXL_PSL_SR_An_SF;