Subject: Re: [PATCH] cxl: Configure the PSL for dual port CAPI on Naples

From: Michael Neuling <[email-masked]>
Date: Wed, 16 Mar 2016 19:55:10 +1100

> > > +		psl_dsnctl |=3D (phb_index << (63-11));
> >=20
> >=20
> > Looking at the psl docs, cappunitid in the dsndctl is bits 6 to 13.
> >   So
> > why 11 here?
> >=20
> Because on POWER8NVL, dsndctl bit 11 =3D=3D phb_index =3D=3D cappunitid.
> Bits 6-10 and 12-13 do not change between POWER8 and POWER8NVL.

OK, can you document that better as what you're doing now is not clear
even when reading the associated docs.

Mikey